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    • 21. 发明申请
    • PROTEASE, DNA ENCODING THE SAME, AND METHOD FOR MANUFACTURING PROTEASE
    • PROTEASE,编码其的DNA,以及制造蛋白质的方法
    • US20100015664A1
    • 2010-01-21
    • US12537259
    • 2009-08-07
    • Yoshitaka KANAYAMAYasuo SakaiTakahiro Hongo
    • Yoshitaka KANAYAMAYasuo SakaiTakahiro Hongo
    • C12P21/02C12N15/11C12N1/20C12N1/21
    • C12N9/52
    • A protease having the following characteristics: (i) a molecular weight of 21,000±1,000 (by SDS-PAGE) and (ii) specific protease activity cutting the Gly-Phe site of a peptide or protein comprising amino acid sequence (1) below, cutting the Gly-Phe site of a peptide or protein comprising amino acid sequence (2) below, or cutting the Ser-Leu site of a peptide or protein comprising amino acid sequence (3) below: Pro-Gln-Gly-Phe-Gln-Gly-Pro(1) (SEQ ID NO: 4) Pro-Ala-Gly-Phe-Ala-Gly-Pro(2) (SEQ ID NO: 5) Gln-Thr-Gln-Ser-Leu-Val-Thr-Pro.(3) (SEQ ID NO: 6) DNA encoding this protease, including vectors containing this DNA, and a method for producing this protease by transforming a cell with this DNA.
    • 具有以下特征的蛋白酶:(i)分子量为21,000±1,000(通过SDS-PAGE)和(ii)切割包含以下氨基酸序列(1)的肽或蛋白质的Gly-Phe位点的特异性蛋白酶活性, 切割包含以下氨基酸序列(2)的肽或蛋白质的Gly-Phe位点,或切割包含以下氨基酸序列(3)的肽或蛋白质的Ser-Leu位点:Pro-Gln-Gly-Phe-Gln -Gly-Pro(1)(SEQ ID NO:4)Pro-Ala-Gly-Phe-Ala-Gly-Pro(2)(SEQ ID NO:5)Gln-Thr-Gln-Ser-Leu-Val-Thr -Pro。 (3)(SEQ ID NO:6)编码该蛋白酶的DNA,包含含有该DNA的载体,以及通过用该DNA转化细胞产生该蛋白酶的方法。
    • 22. 发明授权
    • Display control system for a scan type display apparatus
    • 用于扫描型显示装置的显示控制系统
    • US5579458A
    • 1996-11-26
    • US310992
    • 1994-09-23
    • Hirobumi YokosukaYasuo SakaiKazuo Miyazaki
    • Hirobumi YokosukaYasuo SakaiKazuo Miyazaki
    • G09G3/36G09G3/20G09G5/00G06T1/60
    • G09G3/3644G09G3/3666
    • A display control system for a scan type display apparatus in which a display screen is divided into a plurality of split display regions on a video screen and each display region is scanned in parallel. A dual port memory having a random access port and a serial access port is used as a display memory and display data is inputted through the random access port and outputted through the serial access port. Display addresses for reading out sequentially display data corresponding to each raster of every split display region one by one from the dual port memory are generated and the display data of each of the split display regions read out from the dual port memory are stored into each of the buffer memories. The display data stored in the buffer memories is read out and transferred to the scan type display device.
    • 扫描型显示装置的显示控制系统,其中在视频屏幕上将显示屏划分为多个分割显示区域,并且扫描每个显示区域。 使用具有随机存取端口和串行访问端口的双端口存储器作为显示存储器,并且通过随机存取端口输入显示数据并通过串行访问端口输出。 生成从双端口存储器逐个读出对应于每个分割显示区域的每个光栅的顺序显示数据的显示地址,并且将从双端口存储器读出的每个分割显示区域的显示数据存储在 缓冲存储器。 存储在缓冲存储器中的显示数据被读出并传送到扫描型显示装置。
    • 23. 发明授权
    • Parallel-to-serial signal converting apparatus and image displaying
system using the same
    • 并行到串行信号转换装置和使用它的图像显示系统
    • US5089819A
    • 1992-02-18
    • US416831
    • 1989-10-03
    • Hirobumi YokosukaYasuo Sakai
    • Hirobumi YokosukaYasuo Sakai
    • G09G5/00G09G1/02G09G5/18H03M9/00
    • H03M9/00
    • A parallel-to-serial signal converting apparatus which comprises: a logic circuit for converting first parallel bit signals of a low frequency to be converted to a high frequency serial bit signal into second parallel bit signals having the same frequency as the first parallel bit signals and having information as to whether adjacent two bits of the serial bit signal are equal in level or not; a circuit for adjusting the phase of the second parallel bit signals to form third parallel bit signals whose phases are shifted by a phase difference, successively, in an order of corresponding bits of the serial bit signal, the phase difference being substantially equal to the phase difference between adjacent two bits of the serial bit signal; and a logic circuit for logically processing the third parallel bit signals to obtain the serial bit signal. An image displaying system utilizes the parallel-to-serial signal converting apparatus.
    • 一种并行到串行信号转换装置,包括:逻辑电路,用于将要转换为高频串行位信号的低频的第一并行位信号转换成具有与第一并行位信号相同频率的第二并行位信号 并且具有关于串行位信号的相邻两位是否相等的信息; 用于调整第二并行位信号的相位以形成第三并行位信号的电路,其相位按照串行位信号的相应位的顺序依次相移相位差,相位差基本上等于相位 串行位信号的相邻两位之间的差; 以及用于逻辑处理第三并行位信号以获得串行位信号的逻辑电路。 图像显示系统利用并行到串行信号转换装置。
    • 28. 发明授权
    • Protease, DNA encoding the same, and method for manufacturing protease
    • 蛋白酶,编码相同的DNA,以及制造蛋白酶的方法
    • US07601807B2
    • 2009-10-13
    • US11287307
    • 2005-11-28
    • Yoshitaka KanayamaYasuo SakaiTakahiro Hongo
    • Yoshitaka KanayamaYasuo SakaiTakahiro Hongo
    • C07K1/00
    • C12N9/52
    • A protease having the following characteristics: (i) a molecular weight of 21,000±1,000 (by SDS-PAGE) and (ii) specific protease activity cutting the Gly-Phe site of a peptide or protein comprising amino acid sequence (1) below, cutting the Gly-Phe site of a peptide or protein comprising amino acid sequence (2) below, or cutting the Ser-Leu site of a peptide or protein comprising amino acid sequence (3) below: (1) (SEQ ID NO:4) Pro-Gln-Gly-Phe-Gln-Gly-Pro (2) (SEQ ID NO:5) Pro-Ala-Gly-Phe-Ala-Gly-Pro (3) (SEQ ID NO:6) Gln-Thr-Gln-Ser-Leu-Val-Thr-Pro. DNA encoding this protease, including vectors containing this DNA, and a method for producing this protease by transforming a cell with this DNA.
    • 具有以下特征的蛋白酶:(i)分子量为21,000±1,000(通过SDS-PAGE)和(ii)切割包含以下氨基酸序列(1)的肽或蛋白质的Gly-Phe位点的特异性蛋白酶活性, 切割包含以下氨基酸序列(2)的肽或蛋白质的Gly-Phe位点,或切割包含以下氨基酸序列(3)的肽或蛋白质的Ser-Leu位点:(1)(SEQ ID NO:4 )Pro-Gln-Gly-Phe-Gln-Gly-Pro(2)(SEQ ID NO:5)Pro-Ala-Gly-Phe-Ala-Gly-Pro(3)(SEQ ID NO:6)Gln-Thr -Gln-Ser-Leu-Val-Thr-Pro。 编码该蛋白酶的DNA,包括含有该DNA的载体,以及通过用该DNA转化细胞来生产该蛋白酶的方法。