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21. 发明申请

US20090116290A1 METHODS AND APPARATUSES RELATING TO AUTOMATIC CELL THRESHOLD VOLTAGE MEASUREMENT 有权
标题翻译：关于自动电池电压测量的方法和设备
公开(公告)号：US20090116290A1
公开(公告)日：2009-05-07
申请号：US12352147
申请日：2009-01-12
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/04 , G11C16/06 , G11C7/00
CPC分类号： G11C29/50 , G11C16/04 , G11C16/0483 , G11C16/28 , G11C29/12005 , G11C29/50004
摘要： Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current generator, a plurality of memory cells and a pre-charge bit line reference circuit. If the reference current is greater than the memory cell current, the bit line voltage will increase. Conversely, if the reference current is less than the memory cell current, the bit line voltage will decrease. The reference current is generated in large steps until a comparator, that compares the bit line voltage and a pre-charged bit line reference voltage, is switched. The reference current then generates a current in small steps until the comparator is again switched. The reference current converges on the memory cell current within an accuracy of 10 nA. The memory cell threshold voltage is then determined from the memory cell current. Systems including memory according to an embodiment of the invention are also disclosed.
摘要翻译：公开了用于自动测量存储单元阈值电压的方法和装置。测量电路包括内部参考电流发生器，多个存储单元和预充电位线参考电路。如果参考电流大于存储单元电流，则位线电压将增加。相反，如果参考电流小于存储单元电流，则位线电压将降低。参考电流以大的步长产生，直到比较位线电压和预充电位线参考电压的比较器被切换为止。参考电流然后以小步骤产生电流，直到再次切换比较器。参考电流在10 nA的精度内收敛于存储单元电流。然后从存储单元电流确定存储单元阈值电压。还公开了包括根据本发明的实施例的存储器的系统。

22. 发明授权

US07280413B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07280413B2
公开(公告)日：2007-10-09
申请号：US11124253
申请日：2005-05-09
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C5/14
CPC分类号： G11C16/08 , G11C16/12 , G11C16/30
摘要： A transmission transistor transmitting a drain voltage is connected to an electrically rewritable nonvolatile memory cell. An operation control circuit controls program operation for increasing a threshold voltage of the memory cell, and verify operation which is performed before and after the program operation in order to verify the threshold voltage of the memory cell. A drain switching circuit connects during the verify operation a gate of the transmission transistor to a first voltage line through which a first voltage is supplied, and it connects during the program operation the same to a second voltage line through which a second voltage is supplied. Since the second voltage can be supplied to the transmission transistor only by the switching operation (selecting operation) of the drain switching circuit, the program operation can be started shortly after the verify operation. This can shorten the data write time to the memory cell.
摘要翻译：传输漏极电压的透射晶体管连接到电可重写的非易失性存储单元。操作控制电路控制用于增加存储单元的阈值电压的程序操作，以及验证在编程操作之前和之后执行的操作，以便验证存储器单元的阈值电压。漏极切换电路在验证操作期间将传输晶体管的栅极连接到提供第一电压的第一电压线，并且其在编程操作期间连接到提供第二电压的第二电压线。由于只能通过漏极切换电路的切换操作（选择操作）将第二电压提供给传输晶体管，所以可以在验证操作之后不久开始编程操作。这可以缩短到存储器单元的数据写入时间。

23. 发明授权

US07206232B2 Semiconductor device and source voltage control method 有权
标题翻译：半导体器件和源极电压控制方法
公开(公告)号：US07206232B2
公开(公告)日：2007-04-17
申请号：US11165008
申请日：2005-06-23
申请人： Kazuhide Kurosaki , Shigekazu Yamada , Masaru Yano
发明人： Kazuhide Kurosaki , Shigekazu Yamada , Masaru Yano
IPC分类号： G11C11/34
CPC分类号： G11C16/30
摘要： The precharge circuit is provided for precharging, before programming the data, the voltage of the source line ARVSS commonly connected to the memory cells provided in the same sector. The voltage of the source line ARVSS of the memory cell MC is precharged before programming the data, and the voltage of the source line ARVSS of the memory cell MC is not lowered at the time of programming the data, even if the data programming period is shortened. It is thus possible to prevent the leak current during the programming and program the data into the memory cell MC optimally.
摘要翻译：在对数据进行编程之前，预充电电路用于预充电，该源电压线ARVSS的电压通常连接到同一扇区中提供的存储单元。在对数据进行编程之前，存储单元MC的源极线ARVSS的电压被预充电，并且即使数据编程期间是数据编程时，存储单元MC的源极线ARVSS的电压也不会降低缩短因此，可以在编程期间防止泄漏电流并且将数据最佳地编程到存储单元MC中。

24. 发明申请

US20060176742A1 Semiconductor device and writing method 有权
标题翻译：半导体器件和写入方法
公开(公告)号：US20060176742A1
公开(公告)日：2006-08-10
申请号：US11194023
申请日：2005-07-29
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C7/10
CPC分类号： G11C11/5628 , G11C16/10 , G11C2216/14
摘要： A semiconductor device has a memory cell array including a multi-level memory cell having multiple and different threshold values, a first latch circuit latching information of multiple-word of input information, a second latch circuit latching write information in which the information of the multiple-word of the input information is converted into information according to each level of the multi-level memory cell, a write circuit writing information into the multi-level memory cell on a group basis corresponding to the number of memory cells simultaneously programmable, according to the write information, and a control circuit controlling programming the memory cell array. The information is simultaneously programmed on the group basis into which multiple-word input information is divided, and makes it possible to shorten a program period substantially on a word basis. The program period is not increased, even if programming and verification are repeated several times in programming the multi-level memory cell.
摘要翻译：一种半导体器件具有存储单元阵列，该存储单元阵列包括具有多个和不同阈值的多电平存储单元，第一锁存电路锁存多字输入信息的信息，第二锁存电路锁存写信息，根据多级存储器单元的每个级别将输入信息的字转换为信息，写电路根据与可同时编程的存储单元的数量对应的组，将信息写入多级存储器单元，根据写入信息，以及控制对存储单元阵列进行编程的控制电路。该信息同时被编程在分组多字输入信息的组基础上，并且使得可以基本上基于单词缩短程序周期。即使编程和验证在编程多层存储单元中重复多次，程序周期也不会增加。

25. 发明申请

US20050201159A1 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20050201159A1
公开(公告)日：2005-09-15
申请号：US11124253
申请日：2005-05-09
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C11/34 , G11C11/401 , G11C16/04 , G11C16/08 , G11C16/12 , G11C16/30
CPC分类号： G11C16/08 , G11C16/12 , G11C16/30
摘要： A transmission transistor transmitting a drain voltage is connected to an electrically rewritable nonvolatile memory cell. An operation control circuit controls program operation for increasing a threshold voltage of the memory cell, and verify operation which is performed before and after the program operation in order to verify the threshold voltage of the memory cell. A drain switching circuit connects during the verify operation a gate of the transmission transistor to a first voltage line through which a first voltage is supplied, and it connects during the program operation the same to a second voltage line through which a second voltage is supplied. Since the second voltage can be supplied to the transmission transistor only by the switching operation (selecting operation) of the drain switching circuit, the program operation can be started shortly after the verify operation. This can shorten the data write time to the memory cell.
摘要翻译：传输漏极电压的透射晶体管连接到电可重写的非易失性存储单元。操作控制电路控制用于增加存储单元的阈值电压的程序操作，以及验证在编程操作之前和之后执行的操作，以便验证存储器单元的阈值电压。漏极切换电路在验证操作期间将传输晶体管的栅极连接到提供第一电压的第一电压线，并且其在编程操作期间连接到提供第二电压的第二电压线。由于只能通过漏极切换电路的切换操作（选择操作）将第二电压提供给传输晶体管，所以可以在验证操作之后不久开始编程操作。这可以缩短到存储器单元的数据写入时间。

26. 发明授权

US06400638B1 Wordline driver for flash memory read mode 有权
标题翻译：用于闪存读取模式的字线驱动程序
公开(公告)号：US06400638B1
公开(公告)日：2002-06-04
申请号：US09680344
申请日：2000-10-05
申请人： Shigekazu Yamada , Takao Akaogi , Colin S. Bill
发明人： Shigekazu Yamada , Takao Akaogi , Colin S. Bill
IPC分类号： G11C800
CPC分类号： G11C16/08 , G11C8/08
摘要： The present invention discloses a wordline voltage regulation method and system that provides a predetermined voltage as a wordline voltage to a plurality of wordlines during read mode. A supply voltage (Vcc) is regulated and temperature compensated by a wordline driver circuit to provide the predetermined voltage that is lower in magnitude than the magnitude of the supply voltage (Vcc). The wordline driver circuit is activated by an activation circuit when the read operation is initiated. During the read operation, the wordline driver circuit maintains the predetermined voltage during variations in the supply voltage (Vcc) as well as variations in a process load supplied by the wordline driver circuit.
摘要翻译：本发明公开了一种在读取模式期间向多个字线提供预定电压作为字线电压的字线电压调节方法和系统。电源电压（Vcc）由字线驱动器电路调节和温度补偿，以提供比电源电压（Vcc）的幅度更低的预定电压。当启动读取操作时，字线驱动器电路由激活电路激活。在读取操作期间，字线驱动器电路在电源电压（Vcc）的变化期间维持预定电压以及由字线驱动器电路提供的工艺负载的变化。

27. 发明授权

US06324108B1 Application of external voltage during array VT testing 有权
标题翻译：阵列VT测试期间应用外部电压
公开(公告)号：US06324108B1
公开(公告)日：2001-11-27
申请号：US09667891
申请日：2000-09-22
申请人： Colin S. Bill , Edward V. Bautista, Jr. , Shigekazu Yamada
发明人： Colin S. Bill , Edward V. Bautista, Jr. , Shigekazu Yamada
IPC分类号： G11C700
CPC分类号： G11C29/12
摘要： When an array VT test mode is entered, a predetermined wordline voltage is generated by a wordline voltage supply and supplied to at least one decoder circuit and a voltage control logic circuit. The voltage control logic circuit generates a predetermined control voltage that is directed to the decoder circuits. The predetermined control voltage activates the decoder circuits. A particular decoder circuit is electrically selected to decode at least one respective wordline and transfer the predetermined wordline voltage to the respective wordline. The activated decoder circuits that are not electrically selected are not forward-biased.
摘要翻译：当输入阵列VT测试模式时，由字线电压源产生预定的字线电压，并提供给至少一个解码器电路和电压控制逻辑电路。电压控制逻辑电路产生指向解码器电路的预定控制电压。预定的控制电压激活解码器电路。特定解码器电路被电选择以解码至少一个相应的字线并将预定字线电压传送到相应的字线。没有电选择的激活的解码器电路不是正向偏置的。

28. 发明授权

US06208564B1 High voltage comparator 有权
标题翻译：高电压比较器
公开(公告)号：US06208564B1
公开(公告)日：2001-03-27
申请号：US09429987
申请日：1999-10-29
申请人： Shigekazu Yamada , Yasushi Kasa
发明人： Shigekazu Yamada , Yasushi Kasa
IPC分类号： G11C700
CPC分类号： G11C16/08 , G11C5/143 , G11C16/30 , G11C16/32
摘要： A high voltage comparator circuit quickly identifies the voltage level of the predetermined voltages required for program operations. Through the series of transistors, the precise timing of when the predetermined voltages are at their operating voltage level is identified.
摘要翻译：高电压比较器电路快速识别程序操作所需的预定电压的电压电平。通过一系列晶体管，确定了预定电压何时处于其工作电压电平的精确定时。

29. 发明授权

US09159452B2 Automatic word line leakage measurement circuitry 有权
标题翻译：自动字线泄漏测量电路
公开(公告)号：US09159452B2
公开(公告)日：2015-10-13
申请号：US12271140
申请日：2008-11-14
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06 , G11C29/02 , G11C16/04 , G11C29/12 , G11C29/50
CPC分类号： G11C7/1006 , G11C7/062 , G11C16/04 , G11C16/08 , G11C29/02 , G11C29/025 , G11C2029/1202 , G11C2029/5006
摘要： The present invention is a circuit and method for measuring leakage on the plurality of word lines in a memory device. In one embodiment, a memory device may include a leakage measurement circuit that is coupled to a plurality of word lines of the memory device. The leakage measurement circuit may be operable to generate a reference current and to determine whether a leakage current on one of the plurality of word lines is acceptable relative to the reference current. In another embodiment, a method may include determining whether leakage on one of a plurality of word lines of a memory device is allowable using a circuit in the memory device.
摘要翻译：本发明是用于测量存储装置中的多条字线上的泄漏的电路和方法。在一个实施例中，存储器件可以包括耦合到存储器件的多个字线的泄漏测量电路。泄漏测量电路可以用于产生参考电流并且确定多个字线中的一个字线上的泄漏电流相对于参考电流是否可接受。在另一个实施例中，一种方法可以包括使用存储器件中的电路来确定存储器件的多个字线中的一个字线上的泄漏是否被允许。

30. 发明授权

US08482986B2 Word line drivers in non-volatile memory device and method having a shared power bank and processor-based systems using same 有权
标题翻译：具有共享电源组和使用其的基于处理器的系统的非易失性存储器件和方法中的字线驱动器
公开(公告)号：US08482986B2
公开(公告)日：2013-07-09
申请号：US13550241
申请日：2012-07-16
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06
CPC分类号： G11C16/08 , G11C8/08
摘要： A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The voltage selection circuit may include selectable low pass filters for filtering the supplied voltage supplied to the word lines in the array of memory cells without significantly increasing the overall die-size of the device.
摘要翻译：一种字线驱动器系统，其利用电压选择电路将多个电压中的一个提供给耦合到多个字线控制电路的输出节点。每个字线控制电路耦合到非易失性存储器单元阵列中的相应字线。电压选择电路可以包括可选择的低通滤波器，用于对提供给存储器单元阵列中的字线的提供的电压进行滤波，而不会显着增加器件的整体裸片尺寸。

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