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21. 发明授权

US06555475B1 Arrangement and method for polishing a surface of a semiconductor wafer 有权
公开(公告)号：US06555475B1
公开(公告)日：2003-04-29
申请号：US10164909
申请日：2002-06-07
申请人： Jayanthi Pallinti , Ron Nagahara
发明人： Jayanthi Pallinti , Ron Nagahara
IPC分类号： H01L21302
CPC分类号： B24B37/345 , B24B37/20
摘要： An arrangement for polishing a semiconductor wafer is disclosed. The arrangement includes a plurality of preassembled polishing pad assemblies which can be selectively coupled to, and decoupled from, an actuating mechanism for rotating the polishing pad assemblies. An associated method of polishing a semiconductor wafer is also disclosed.

22. 发明授权

US06503828B1 Process for selective polishing of metal-filled trenches of integrated circuit structures 有权
标题翻译：用于选择性抛光集成电路结构的金属填充沟槽的工艺
公开(公告)号：US06503828B1
公开(公告)日：2003-01-07
申请号：US09882124
申请日：2001-06-14
申请人： Ronald J. Nagahara , James J. Xie , Akihisa Ueno , Jayanthi Pallinti
发明人： Ronald J. Nagahara , James J. Xie , Akihisa Ueno , Jayanthi Pallinti
IPC分类号： H01L214763
CPC分类号： H01L21/3212 , H01L21/7684
摘要： The invention provides a process for selectively polishing a main electrically conductive layer of an integrated circuit structure by the steps of forming a polishing barrier layer over depressed regions of the main electrically conductive layer; and polishing the portion of the main electrically conductive layer not covered by the polishing barrier layer. The integrated circuit structure treated by the process of the invention contains one or more openings in a layer of dielectric material, and the main electrically conductive layer fills the one or more openings such that the depressed regions of the main electrically conductive layer overlie said one or more openings.
摘要翻译：本发明提供了一种通过在主导电层的凹陷区域上形成抛光阻挡层的步骤来选择性地研磨集成电路结构的主导电层的工艺; 并且抛光未被抛光阻挡层覆盖的主导电层的部分。通过本发明的方法处理的集成电路结构在介电材料层中包含一个或多个开口，并且主导电层填充一个或多个开口，使得主导电层的凹陷区域覆盖所述一个或多个更多开口

23. 发明授权

US06391768B1 Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure 有权
标题翻译：用于CMP去除多余沟槽或通过填充金属的方法，其抑制在集成电路结构的氧化物表面上形成凹陷区域
公开(公告)号：US06391768B1
公开(公告)日：2002-05-21
申请号：US09703616
申请日：2000-10-30
申请人： Dawn M. Lee , Jayanthi Pallinti , Weidan Li , Ming-Yi Lee
发明人： Dawn M. Lee , Jayanthi Pallinti , Weidan Li , Ming-Yi Lee
IPC分类号： H01L214763
CPC分类号： H01L21/7684
摘要： A process-is disclosed for planarizing an integrated circuit structure by chemical mechanical polishing (CMP) after filling, with at least one metal, a plurality of trenches and/or vias formed in a silicon oxide layer on the integrated circuit structure. The process, which is capable of inhibiting formation of concave surface portions on the silicon oxide surface, during the CMP process, in regions where said trenches and/or vias are closely spaced apart, comprises forming, over a layer of silicon oxide of an integrated circuit structure, an antireflective coating (ARC) layer of dielectric material capable of functioning as a stop layer in a CMP process to remove metal; and using this ARC layer as a stop layer to assist in removal of excess metal used to fill trenches and/or vias formed in the oxide layer. The particular material chosen for the ARC layer should have a lower etch rate, in a CMP process to remove metal, than does the underlying oxide dielectric layer. Trenches and/or vias are formed through the ARC layer and the oxide dielectric layer. These trenches and/or vias are then filled by depositing at least one metal layer over the ARC layer. Excess trench and/or via filler metal is then removed from the top surface of the ARC layer by subjecting the metal to a CMP step which is selective to the ARC layer, thereby permitting the ARC layer to function as a CMP stop layer which protects the underlying oxide dielectric layer from exposure to the CMP process. Since the ARC layer has a lower etch rate, in the CMP process to remove metal, than does the oxide dielectric layer, the formation of dished or concave regions in the surface is inhibited, including those regions where the trenches and/or vias are closely spaced apart.
摘要翻译：公开了一种用于在填充之后通过化学机械抛光（CMP）对集成电路结构进行平面化的工艺，其中至少一个金属，形成在集成电路结构上的氧化硅层中的多个沟槽和/或通孔。在CMP工艺期间，能够阻止在氧化硅表面上形成凹面部分的工艺，其中所述沟槽和/或通孔紧密间隔开的区域中，包括在集成的电路结构，能够在CMP工艺中用作去除金属的停止层的介电材料的抗反射涂层（ARC）层; 并且使用该ARC层作为停止层来辅助去除用于填充形成在氧化物层中的沟槽和/或通孔的多余金属。选择用于ARC层的特定材料在CMP工艺中应该具有比底层氧化物介电层更低的去除金属的蚀刻速率。通过ARC层和氧化物介电层形成沟槽和/或通孔。然后通过在ARC层上沉积至少一个金属层来填充这些沟槽和/或通孔。然后通过对金属进行对ARC层有选择性的CMP步骤，从ARC层的顶表面去除过量的沟槽和/或通孔填充金属，从而允许ARC层用作CMP停止层，其保护潜在的氧化物介电层暴露于CMP工艺。由于ARC层具有较低的蚀刻速率，所以在除去金属的CMP工艺中，与氧化物电介质层相比，抑制了表面上的凹陷或凹陷区域的形成，包括沟槽和/或通孔密切的区域间隔开

24. 发明授权

US6060370A Method for shallow trench isolations with chemical-mechanical polishing 失效
标题翻译：化学机械抛光浅沟槽隔离方法
公开(公告)号：US6060370A
公开(公告)日：2000-05-09
申请号：US98635
申请日：1998-06-16
申请人： Shouli Steve Hsia , Yanhua Wang , Jayanthi Pallinti
发明人： Shouli Steve Hsia , Yanhua Wang , Jayanthi Pallinti
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229
摘要： A process for fabricating a trench filled with an insulating material in a surface of an integrated circuit substrate is described. One step of the process includes defining a masking layer on a composite layered stack above a region to be protected on the integrated circuit substrate surface. The composite layered stack includes a layer of a first material and a polishing stopping layer. The layer of the first material has a polishing rate by chemical mechanical polishing that is greater than a polishing rate by chemical mechanical polishing of the insulating material. Another step of the process includes etching through the composite layered stack and the integrated circuit substrate to form the trench in the integrated circuit substrate surface and depositing the insulating material on the integrated circuit substrate surface such that the trench is filled with the insulating material. A yet another step of the process includes polishing the integrated circuit substrate surface to remove a substantial portion of the composite layered stack and a portion of the insulating material adjacent to the composite layered stack at about a same rate. The polishing step facilitates in forming a substantially planar surface of the insulating material above the trench and reducing a likelihood of forming of a concave region near a middle region of the surface of the insulating material. The concave region recesses inwardly into the surface of the insulating material in the trench.
摘要翻译：描述了在集成电路基板的表面中制造填充有绝缘材料的沟槽的工艺。该方法的一个步骤包括在集成电路基板表面上待保护的区域上的复合分层堆叠上限定掩模层。复合层叠堆叠包括第一材料层和抛光停止层。第一材料的层通过化学机械抛光具有比通过绝缘材料的化学机械抛光的抛光速率大的抛光速率。该方法的另一步骤包括通过复合层叠堆叠和集成电路衬底进行蚀刻以在集成电路衬底表面中形成沟槽，并将绝缘材料沉积在集成电路衬底表面上，使得沟槽填充有绝缘材料。该方法的另一步骤包括抛光集成电路衬底表面以大致相同的速率去除复合层叠堆叠的大部分和与复合层叠堆叠相邻的绝缘材料的一部分。抛光步骤有助于在沟槽上方形成绝缘材料的基本平坦的表面，并减少在绝缘材料的表面的中间区域附近形成凹陷区域的可能性。凹入区域向内凹入沟槽中绝缘材料的表面。

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