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1. 发明授权

US06424019B1 Shallow trench isolation chemical-mechanical polishing process 有权
标题翻译：浅沟隔离化学机械抛光工艺
公开(公告)号：US06424019B1
公开(公告)日：2002-07-23
申请号：US09507042
申请日：2000-02-18
申请人： Shouli Steve Hsia , Yanhua Wang , Jayanthi Pallinti
发明人： Shouli Steve Hsia , Yanhua Wang , Jayanthi Pallinti
IPC分类号： H01C2900
CPC分类号： H01L21/76229
摘要： A process for fabricating a trench filled with an insulating material in a surface of an integrated circuit substrate is described. One step of the process includes defining a masking layer on a composite layered stack above a region to be protected on the integrated circuit substrate surface. The composite layered stack includes a layer of a first material and a polishing stopping layer. The layer of the first material has a polishing rate by chemical mechanical polishing that is greater than a polishing rate by chemical mechanical polishing of the insulating material. Another step of the process includes etching through the composite layered stack and the integrated circuit substrate to form the trench in the integrated circuit substrate surface and depositing the insulating material on the integrated circuit substrate surface such that the trench is filled with the insulating material. A yet another step of the process includes polishing the integrated circuit substrate surface to remove a substantial portion of the composite layered stack and a portion of the insulating material adjacent to the composite layered stack at about a same rate. The polishing step facilitates in forming a substantially planar surface of the insulating material above the trench and reducing a likelihood of forming of a concave region near a middle region of the surface of the insulating material. The concave region recesses inwardly into the surface of the insulating material in the trench.
摘要翻译：描述了在集成电路基板的表面中制造填充有绝缘材料的沟槽的工艺。该方法的一个步骤包括在集成电路基板表面上待保护的区域上的复合分层堆叠上限定掩模层。复合层叠堆叠包括第一材料层和抛光停止层。第一材料的层通过化学机械抛光具有比通过绝缘材料的化学机械抛光的抛光速率大的抛光速率。该方法的另一步骤包括通过复合层叠堆叠和集成电路衬底进行蚀刻以在集成电路衬底表面中形成沟槽，并将绝缘材料沉积在集成电路衬底表面上，使得沟槽填充有绝缘材料。该方法的另一步骤包括抛光集成电路衬底表面以大致相同的速率去除复合层叠堆叠的大部分和与复合层叠堆叠相邻的绝缘材料的一部分。抛光步骤有助于在沟槽上方形成绝缘材料的基本平坦的表面，并减少在绝缘材料的表面的中间区域附近形成凹陷区域的可能性。凹入区域向内凹入沟槽中绝缘材料的表面。

2. 发明授权

US6060370A Method for shallow trench isolations with chemical-mechanical polishing 失效
标题翻译：化学机械抛光浅沟槽隔离方法
公开(公告)号：US6060370A
公开(公告)日：2000-05-09
申请号：US98635
申请日：1998-06-16
申请人： Shouli Steve Hsia , Yanhua Wang , Jayanthi Pallinti
发明人： Shouli Steve Hsia , Yanhua Wang , Jayanthi Pallinti
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229
摘要： A process for fabricating a trench filled with an insulating material in a surface of an integrated circuit substrate is described. One step of the process includes defining a masking layer on a composite layered stack above a region to be protected on the integrated circuit substrate surface. The composite layered stack includes a layer of a first material and a polishing stopping layer. The layer of the first material has a polishing rate by chemical mechanical polishing that is greater than a polishing rate by chemical mechanical polishing of the insulating material. Another step of the process includes etching through the composite layered stack and the integrated circuit substrate to form the trench in the integrated circuit substrate surface and depositing the insulating material on the integrated circuit substrate surface such that the trench is filled with the insulating material. A yet another step of the process includes polishing the integrated circuit substrate surface to remove a substantial portion of the composite layered stack and a portion of the insulating material adjacent to the composite layered stack at about a same rate. The polishing step facilitates in forming a substantially planar surface of the insulating material above the trench and reducing a likelihood of forming of a concave region near a middle region of the surface of the insulating material. The concave region recesses inwardly into the surface of the insulating material in the trench.
摘要翻译：描述了在集成电路基板的表面中制造填充有绝缘材料的沟槽的工艺。该方法的一个步骤包括在集成电路基板表面上待保护的区域上的复合分层堆叠上限定掩模层。复合层叠堆叠包括第一材料层和抛光停止层。第一材料的层通过化学机械抛光具有比通过绝缘材料的化学机械抛光的抛光速率大的抛光速率。该方法的另一步骤包括通过复合层叠堆叠和集成电路衬底进行蚀刻以在集成电路衬底表面中形成沟槽，并将绝缘材料沉积在集成电路衬底表面上，使得沟槽填充有绝缘材料。该方法的另一步骤包括抛光集成电路衬底表面以大致相同的速率去除复合层叠堆叠的大部分和与复合层叠堆叠相邻的绝缘材料的一部分。抛光步骤有助于在沟槽上方形成绝缘材料的基本平坦的表面，并减少在绝缘材料的表面的中间区域附近形成凹陷区域的可能性。凹入区域向内凹入沟槽中绝缘材料的表面。

3. 发明授权

US09171220B2 Apparatus and method for tracking contour of moving object, and apparatus and method for analyzing myocardial motion 有权
标题翻译：用于跟踪运动物体轮廓的装置和方法，以及用于分析心肌运动的装置和方法
公开(公告)号：US09171220B2
公开(公告)日：2015-10-27
申请号：US13553308
申请日：2012-07-19
申请人： Yanhua Wang , Chao Cong , Yanli Wang , Shaobin Wang , Qiuying Dong
发明人： Yanhua Wang , Chao Cong , Yanli Wang , Shaobin Wang , Qiuying Dong
IPC分类号： G06K9/00 , G06K9/32 , G06T7/20 , A61B6/00 , A61B8/08 , A61B6/03 , A61B5/055
CPC分类号： G06K9/00127 , A61B5/055 , A61B6/032 , A61B6/037 , A61B6/503 , A61B6/5217 , A61B8/0883 , A61B8/5223 , G06K9/3233 , G06T7/20 , G06T7/246 , G06T2207/20168 , G06T2207/30048
摘要： A moving object contour tracking apparatus includes a contour tracking section for performing, by taking an initial contour of the moving object in a predetermined image slice as a starting contour, contour tracking in a first time direction to acquire a first contour of the moving object and contour tracking in a second time direction to acquire a second contour of the moving object in each image slice; a contour comparison section for calculating, in the predetermined image slice, a similarity between the first contour and the initial contour and a similarity between the second contour and the initial contour; and a contour correction section for taking the contours in the image slices that are acquired in a contour tracking direction corresponding to the greater one of the two similarities as the contours of the moving object in the respective image slices.
摘要翻译：运动物体轮廓跟踪装置包括轮廓跟踪部分，用于通过以预定图像片段中的运动对象的初始轮廓作为起始轮廓，在第一时间方向上进行轮廓跟踪，以获取运动物体的第一轮廓;以及在第二时间方向上的轮廓跟踪以获取每个图像切片中的移动物体的第二轮廓; 轮廓比较部分，用于在预定图像切片中计算第一轮廓和初始轮廓之间的相似度以及第二轮廓和初始轮廓之间的相似度; 以及轮廓校正部，用于将在与两个相似度中较大的一个相对应的轮廓跟踪方向中获取的图像切片中的轮廓作为各个图像切片中的移动物体的轮廓。

4. 发明申请

US20120281452A1 RESISTIVE RANDOM MEMORY CELL AND MEMORY 有权
标题翻译：电阻随机存储器和存储器
公开(公告)号：US20120281452A1
公开(公告)日：2012-11-08
申请号：US13502832
申请日：2011-06-30
申请人： Zongliang Huo , Ming Liu , Manhong Zhang , Yanhua Wang , Shibing Long
发明人： Zongliang Huo , Ming Liu , Manhong Zhang , Yanhua Wang , Shibing Long
IPC分类号： H01L45/00 , G11C11/00
CPC分类号： H01L27/2409 , H01L27/2463
摘要： The present disclosure provides a resistive random memory cell and a resistive random memory. The resistive random memory cell comprises an upper electrode, a resistive layer, an intermediate electrode, an asymmetric tunneling barrier layer, and a lower electrode. The upper electrode, the resistive layer, and the intermediate electrode constitute a resistive storage portion. The intermediate electrode, the asymmetric tunneling barrier layer, and the lower electrode constitute a selection portion. The resistive storage portion and the selection portion share the intermediate electrode. The selection portion may be disposed above or under the resistive storage portion. The asymmetric tunneling barrier layer comprises at least two materials having different barrier heights, and is configured for rectifying forward tunneling current and reverse tunneling current flowing through the resistive random memory cell. The present disclosure uses the asymmetric tunneling barrier layer for rectifying, so as to enable selection of the resistive random memory cell. The method for manufacturing the asymmetric tunneling barrier layer does not involve doping or high-temperature annealing processes, and the thickness of the asymmetric tunneling barrier layer is relatively small, which helps 3D high-density integration of the resistive random memory.
摘要翻译：本公开提供了电阻随机存储器单元和电阻随机存储器。电阻随机存储单元包括上电极，电阻层，中间电极，不对称隧道势垒层和下电极。上电极，电阻层和中间电极构成电阻存储部。中间电极，不对称隧道势垒层和下电极构成选择部分。电阻存储部分和选择部分共享中间电极。选择部分可以设置在电阻存储部分的上方或下方。非对称隧道势垒层包括具有不同势垒高度的至少两种材料，并且被配置用于整流流过电阻随机存储单元的正向隧穿电流和反向隧穿电流。本公开使用非对称隧道势垒层进行整流，以便能够选择电阻随机存储单元。制造不对称隧道势垒层的方法不涉及掺杂或高温退火工艺，并且不对称隧道势垒层的厚度相对较小，这有助于电阻随机存储器的3D高密度集成。

5. 发明授权

US06747318B1 Buried channel devices and a process for their fabrication simultaneously with surface channel devices to produce transistors and capacitors with multiple electrical gate oxides 有权
标题翻译：掩埋通道器件及其与表面沟道器件同时制造的工艺，以生产具有多个电栅极氧化物的晶体管和电容器
公开(公告)号：US06747318B1
公开(公告)日：2004-06-08
申请号：US10020304
申请日：2001-12-13
申请人： Ravindra M. Kapre , Tommy Hsiao , Yanhua Wang , Kyungjin Min
发明人： Ravindra M. Kapre , Tommy Hsiao , Yanhua Wang , Kyungjin Min
IPC分类号： H01L2994
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823892 , H01L29/7838 , H01L29/94
摘要： A method for fabricating buried channel NMOS devices and the devices themselves are disclosed. These buried channel NMOS devices are fabricated with a p-type substrate, an n-type implant in the top portion (approximately 400 to 1000 Å deep) of the substrate, and an insulating gate dielectric above the n-type implant. An n-type or p-type doped polysilicon gate electrode is formed on top of the insulating gate dielectric. The n-type implant region is doped in such a way that it is depleted of charge carriers when the device's gate electrode is at the same potential as the well (zero bias). When the gate electrode is biased +Ve with respect to the device's well substrate a conducting channel of mobile electrons is formed in a portion of the buried layer. This type of biasing is known as inversion bias since the charge carriers are of the opposite type than the p-well. Under inversion bias, the buried channel silicon region is partially depleted of charge carriers, which effectively adds to the thickness of the gate dielectric layer. A capacitor or transistor fabricated according to this buried channel teaching behaves in a manner electrically equivalent to a capacitor or transistor fabricated with a thicker dielectric. PMOS transistors and capacitors can be constructed according to the present invention in a manner similar to that described for NMOS transistors and capacitors by substituting n-type doping for p-type and visa versa. This leads to the fabrication of CMOS devices with multiple effective dielectric thicknesses on the same substrate.
摘要翻译：公开了一种用于制造掩埋沟道NMOS器件和器件本身的方法。这些掩埋沟道NMOS器件由p型衬底，衬底的顶部（约400至1000深）中的n型注入器以及n型注入器之上的绝缘栅极电介质制成。在绝缘栅极电介质的顶部上形成n型或p型掺杂多晶硅栅电极。掺杂n型注入区的方式是当器件的栅电极处于与阱相同的电位（零偏压）时，其耗尽电荷载流子。当栅电极相对于器件的阱衬底偏置+ Ve时，移动电子的导电沟道形成在掩埋层的一部分中。这种偏置称为反向偏置，因为电荷载体与p阱相反。在反向偏置下，掩埋沟道硅区域部分耗尽电荷载流子，这有效地增加了栅极介电层的厚度。根据该掩埋通道示教制造的电容器或晶体管以与电介质较厚的电容器或晶体管电气等效的方式起作用。根据本发明，PMOS晶体管和电容器可以以类似于对NMOS晶体管和电容器描述的方式构造，通过用n型掺杂代替p型，反之亦然。这导致在同一衬底上制造具有多个有效介电厚度的CMOS器件。

6. 发明授权

US08665631B2 Resistive random memory cell and memory 有权
标题翻译：电阻随机存储单元和存储器
公开(公告)号：US08665631B2
公开(公告)日：2014-03-04
申请号：US13502832
申请日：2011-06-30
申请人： Zongliang Huo , Ming Liu , Manhong Zhang , Yanhua Wang , Shibing Long
发明人： Zongliang Huo , Ming Liu , Manhong Zhang , Yanhua Wang , Shibing Long
IPC分类号： G11C11/00
CPC分类号： H01L27/2409 , H01L27/2463
摘要： The present disclosure provides a resistive random memory cell and a resistive random memory. The resistive random memory cell comprises an upper electrode, a resistive layer, an intermediate electrode, an asymmetric tunneling barrier layer, and a lower electrode. The upper electrode, the resistive layer, and the intermediate electrode constitute a resistive storage portion. The intermediate electrode, the asymmetric tunneling barrier layer, and the lower electrode constitute a selection portion. The resistive storage portion and the selection portion share the intermediate electrode. The selection portion may be disposed above or under the resistive storage portion. The asymmetric tunneling barrier layer comprises at least two materials having different barrier heights, and is configured for rectifying forward tunneling current and reverse tunneling current flowing through the resistive random memory cell. The present disclosure uses the asymmetric tunneling barrier layer for rectifying, so as to enable selection of the resistive random memory cell. The method for manufacturing the asymmetric tunneling barrier layer does not involve doping or high-temperature annealing processes, and the thickness of the asymmetric tunneling barrier layer is relatively small, which helps 3D high-density integration of the resistive random memory.
摘要翻译：本公开提供了电阻随机存储器单元和电阻随机存储器。电阻随机存储单元包括上电极，电阻层，中间电极，不对称隧道势垒层和下电极。上电极，电阻层和中间电极构成电阻存储部。中间电极，不对称隧道势垒层和下电极构成选择部分。电阻存储部分和选择部分共享中间电极。选择部分可以设置在电阻存储部分的上方或下方。非对称隧道势垒层包括具有不同势垒高度的至少两种材料，并且被配置用于整流流过电阻随机存储单元的正向隧穿电流和反向隧穿电流。本公开使用非对称隧道势垒层进行整流，以便能够选择电阻随机存储单元。制造不对称隧道势垒层的方法不涉及掺杂或高温退火工艺，并且不对称隧道势垒层的厚度相对较小，这有助于电阻随机存储器的3D高密度集成。

7. 发明授权

US08735245B2 Metal oxide resistive switching memory and method for manufacturing same 有权
标题翻译：金属氧化物电阻式开关存储器及其制造方法
公开(公告)号：US08735245B2
公开(公告)日：2014-05-27
申请号：US13510467
申请日：2011-06-30
申请人： Hangbing Lv , Ming Liu , Shibing Long , Qi Liu , Yanhua Wang , Jiebin Niu
发明人： Hangbing Lv , Ming Liu , Shibing Long , Qi Liu , Yanhua Wang , Jiebin Niu
IPC分类号： H01L21/8239 , G11C11/21
CPC分类号： H01L27/101 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16
摘要： The present disclosure relates to the microelectronics field, and particularly, to a metal oxide resistive switching memory and a method for manufacturing the same. The method may comprise: forming a W-plug lower electrode above a MOS device; sequentially forming a cap layer, a first dielectric layer, and an etching block layer on the W-plug lower electrode; etching the etching block layer, the first dielectric layer, and the cap layer to form a groove for a first level of metal wiring; sequentially forming a metal oxide layer, an upper electrode layer, and a composite layer of a diffusion block layer/a seed copper layer/a plated copper layer in the groove for the first level of metal wiring; patterning the upper electrode layer and the composite layer by CMP, to form a memory cell and the first level of metal wiring in the groove in the first dielectric layer; and performing subsequent processes to complete the metal oxide resistive switching memory. According to the present disclosure, the manufacture process can be simplified, without incorporating additional exposure steps in the standard process, resulting in advantages such as reduced cost.
摘要翻译：本公开涉及微电子领域，特别涉及金属氧化物电阻式开关存储器及其制造方法。该方法可以包括：在MOS器件之上形成W形插塞下电极; 在W型插塞下电极上依次形成覆盖层，第一电介质层和蚀刻阻挡层; 蚀刻蚀刻阻挡层，第一介电层和盖层，以形成用于第一级金属布线的凹槽; 在用于第一级金属布线的槽中依次形成金属氧化物层，上电极层和扩散阻挡层/种子铜层/镀覆铜层的复合层; 通过CMP图案化上电极层和复合层，以在第一介电层中的沟槽中形成存储单元和第一级金属布线; 以及执行后续处理以完成金属氧化物电阻式切换存储器。根据本公开，可以简化制造过程，而不在标准方法中引入额外的暴露步骤，导致诸如降低成本的优点。

8. 发明授权

US08346239B2 Methods, systems, and computer program products for silence insertion descriptor (SID) conversion 有权
标题翻译：用于静音插入描述符（SID）转换的方法，系统和计算机程序产品
公开(公告)号：US08346239B2
公开(公告)日：2013-01-01
申请号：US11965994
申请日：2007-12-28
申请人： Yanhua Wang , Philip Abraham
发明人： Yanhua Wang , Philip Abraham
IPC分类号： H04Q7/20
CPC分类号： H04W88/181
摘要： Methods, systems, and computer program products for silence insertion descriptor (SID) conversion are disclosed. According to one aspect, the subject matter described herein includes a method for silence insertion descriptor (SID) conversion. The method includes receiving a wireless frame, the frame identifying a first node as a frame source and a second node as a frame destination; determining whether tandem-free operation (TFO) is applicable; responsive to a determination that TFO is applicable, determining whether the frame is a SID frame; responsive to a determination that the frame is a SID frame, determining whether the SID format used by the first node is incompatible with the SID format used by the second node; and responsive to a determination that the SID format used by the first node is incompatible with the SID format used by the second node, converting the SID frame from the SID format used by the first node to the SID format used by the second node.
摘要翻译：公开了用于静音插入描述符（SID）转换的方法，系统和计算机程序产品。根据一个方面，本文描述的主题包括用于静音插入描述符（SID）转换的方法。所述方法包括接收无线帧，将所述帧识别为第一节点作为帧源，将所述第二节点标识为帧目的地; 确定无串联运行（TFO）是否适用; 响应于TFO可适用的确定，确定该帧是否是SID帧; 响应于所述帧是SID帧的确定，确定由所述第一节点使用的SID格式是否与由所述第二节点使用的SID格式不兼容; 并且响应于第一节点使用的SID格式与第二节点使用的SID格式不兼容的确定，将SID帧从第一节点使用的SID格式转换为第二节点使用的SID格式。

9. 发明授权

US09314161B2 Moving object contour extraction apparatus, left ventricle image segmentation apparatus, moving object contour extraction method and left ventricle image segmentation method 有权
标题翻译：移动物体轮廓提取装置，左心室图像分割装置，移动物体轮廓提取方法和左心室图像分割方法
公开(公告)号：US09314161B2
公开(公告)日：2016-04-19
申请号：US13553022
申请日：2012-07-19
申请人： Yanhua Wang , Chao Cong , Yanli Wang , Shaobin Wang
发明人： Yanhua Wang , Chao Cong , Yanli Wang , Shaobin Wang
IPC分类号： G06K9/00 , A61B5/00 , G06T7/00 , G06T7/20 , G06T7/60 , A61B5/055 , A61B6/03 , A61B6/00 , A61B8/08 , A61B8/13
CPC分类号： A61B5/0073 , A61B5/0044 , A61B5/055 , A61B6/032 , A61B6/037 , A61B6/503 , A61B8/0883 , A61B8/13 , G06T7/12 , G06T7/246 , G06T7/62 , G06T2207/30048
摘要： According to one embodiment, a moving object contour extraction apparatus includes a contour acquisition unit and a contour correction unit. The contour acquisition unit is configured to acquire a contour of a moving object in each image slice. The contour correction unit is configured to correct the contours of the moving object in image slices of at least one image slice time series based on motion trend information of the moving object in each of a plurality of image slice time series.
摘要翻译：根据一个实施例，移动物体轮廓提取装置包括轮廓获取单元和轮廓校正单元。轮廓获取单元被配置为获取每个图像切片中的移动物体的轮廓。轮廓校正单元被配置为基于多个图像切片时间序列中的每一个中的运动对象的运动趋势信息来校正至少一个图像切片时间序列的图像切片中的运动对象的轮廓。

10. 发明申请

US20120305883A1 METAL OXIDE RESISTIVE SWITCHING MEMORY AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：金属氧化物电阻开关存储器及其制造方法
公开(公告)号：US20120305883A1
公开(公告)日：2012-12-06
申请号：US13510467
申请日：2011-06-30
申请人： Hangbing Lv , Ming Liu , Shibing Long , Qi Liu , Yanhua Wang , Jiebin Niu
发明人： Hangbing Lv , Ming Liu , Shibing Long , Qi Liu , Yanhua Wang , Jiebin Niu
IPC分类号： H01L47/00 , H01L45/00
CPC分类号： H01L27/101 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16
摘要： The present disclosure relates to the microelectronics field, and particularly, to a metal oxide resistive switching memory and a method for manufacturing the same. The method may comprise: forming a W-plug lower electrode above a MOS device; sequentially forming a cap layer, a first dielectric layer, and an etching block layer on the W-plug lower electrode; etching the etching block layer, the first dielectric layer, and the cap layer to form a groove for a first level of metal wiring; sequentially forming a metal oxide layer, an upper electrode layer, and a composite layer of a diffusion block layer/a seed copper layer/a plated copper layer in the groove for the first level of metal wiring; patterning the upper electrode layer and the composite layer by CMP, to form a memory cell and the first level of metal wiring in the groove in the first dielectric layer; and performing subsequent processes to complete the metal oxide resistive switching memory. According to the present disclosure, the manufacture process can be simplified, without incorporating additional exposure steps in the standard process, resulting in advantages such as reduced cost.
摘要翻译：本公开涉及微电子领域，特别涉及金属氧化物电阻式开关存储器及其制造方法。该方法可以包括：在MOS器件之上形成W形插塞下电极; 在W型插塞下电极上依次形成覆盖层，第一电介质层和蚀刻阻挡层; 蚀刻蚀刻阻挡层，第一介电层和盖层，以形成用于第一级金属布线的凹槽; 在用于第一级金属布线的槽中依次形成金属氧化物层，上电极层和扩散阻挡层/种子铜层/镀覆铜层的复合层; 通过CMP图案化上电极层和复合层，以在第一介电层中的沟槽中形成存储单元和第一级金属布线; 以及执行后续处理以完成金属氧化物电阻式切换存储器。根据本公开，可以简化制造过程，而不在标准方法中引入额外的暴露步骤，导致诸如降低成本的优点。

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