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21. 发明申请

US20120266008A1 SYSTEM-WIDE POWER MANAGEMENT CONTROL VIA CLOCK DISTRIBUTION NETWORK 有权
标题翻译：通过时钟分配网络进行系统的电源管理控制
公开(公告)号：US20120266008A1
公开(公告)日：2012-10-18
申请号：US13085879
申请日：2011-04-13
申请人： Paul W. Coteus , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Gerard V. Kopcsay , Thomas A. Liebsch , Don D. Reed
发明人： Paul W. Coteus , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Gerard V. Kopcsay , Thomas A. Liebsch , Don D. Reed
IPC分类号： G06F1/12
CPC分类号： G06F1/329 , G06F1/10 , G06F1/12 , G06F1/206 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D10/24
摘要： An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.
摘要翻译：一种用于自动控制包括多个处理器的并行计算系统的功耗的装置，方法和计算机程序产品。计算设备向并行计算系统发出命令。时钟脉冲宽度调制器对系统时钟信号中的命令进行编码，以分配给多个处理器。并行计算系统中的多个处理器接收包括编码命令的系统时钟信号，并根据编码命令调整功耗。

22. 发明授权

US09037892B2 System-wide power management control via clock distribution network 有权
标题翻译：通过时钟分配网络进行全系统的电源管理控制
公开(公告)号：US09037892B2
公开(公告)日：2015-05-19
申请号：US13085879
申请日：2011-04-13
申请人： Paul W. Coteus , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Gerard V. Kopcsay , Thomas A. Liebsch , Don D. Reed
发明人： Paul W. Coteus , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Gerard V. Kopcsay , Thomas A. Liebsch , Don D. Reed
IPC分类号： G06F1/04 , G06F1/12 , G06F1/32 , G06F1/10 , G06F1/20
CPC分类号： G06F1/329 , G06F1/10 , G06F1/12 , G06F1/206 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D10/24
摘要： An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.
摘要翻译：一种用于自动控制包括多个处理器的并行计算系统的功耗的装置，方法和计算机程序产品。计算设备向并行计算系统发出命令。时钟脉冲宽度调制器对系统时钟信号中的命令进行编码，以分配给多个处理器。并行计算系统中的多个处理器接收包括编码命令的系统时钟信号，并根据编码命令调整功耗。

23. 发明授权

US09507647B2 Cache as point of coherence in multiprocessor system 有权
标题翻译：缓存作为多处理器系统中的一致性点
公开(公告)号：US09507647B2
公开(公告)日：2016-11-29
申请号：US13008531
申请日：2011-01-18
申请人： Matthias A. Blumrich , Luis H. Ceze , Dong Chen , Alan Gara , Phlip Heidelberger , Martin Ohmacht , Burkhard Steinmacher-Burow , Xiaotong Zhuang
发明人： Matthias A. Blumrich , Luis H. Ceze , Dong Chen , Alan Gara , Phlip Heidelberger , Martin Ohmacht , Burkhard Steinmacher-Burow , Xiaotong Zhuang
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/52 , G06F12/08
CPC分类号： G06F9/524 , G06F12/08
摘要： In a multiprocessor system, a conflict checking mechanism is implemented in the L2 cache memory. Different versions of speculative writes are maintained in different ways of the cache. A record of speculative writes is maintained in the cache directory. Conflict checking occurs as part of directory lookup. Speculative versions that do not conflict are aggregated into an aggregated version in a different way of the cache. Speculative memory access requests do not go to main memory.
摘要翻译：在多处理器系统中，在L2高速缓冲存储器中实现冲突检查机制。不同版本的推测性写入以不同的方式保存在缓存中。高速缓存目录中保留了推测性写入记录。冲突检查作为目录查找的一部分发生。不冲突的推测版本以不同的缓存方式聚合成聚合版本。推测内存访问请求不会转到主内存。

24. 发明申请

US20110219188A1 CACHE AS POINT OF COHERENCE IN MULTIPROCESSOR SYSTEM 有权
标题翻译： CACHE作为多处理器系统中的一致性点
公开(公告)号：US20110219188A1
公开(公告)日：2011-09-08
申请号：US13008531
申请日：2011-01-18
申请人： Matthias A. Blumrich , Luis H. Ceze , Dong Chen , Alan Gara , Philip Heidelberger , Martin Ohmarcht , Burkhard Steinmacher-Burow , Zhuang Xiaotong
发明人： Matthias A. Blumrich , Luis H. Ceze , Dong Chen , Alan Gara , Philip Heidelberger , Martin Ohmarcht , Burkhard Steinmacher-Burow , Zhuang Xiaotong
IPC分类号： G06F12/08
CPC分类号： G06F9/524 , G06F12/08
摘要： In a multiprocessor system, a conflict checking mechanism is implemented in the L2 cache memory. Different versions of speculative writes are maintained in different ways of the cache. A record of speculative writes is maintained in the cache directory. Conflict checking occurs as part of directory lookup. Speculative versions that do not conflict are aggregated into an aggregated version in a different way of the cache. Speculative memory access requests do not go to main memory.
摘要翻译：在多处理器系统中，在L2高速缓冲存储器中实现冲突检查机制。不同版本的推测性写入以不同的方式保存在缓存中。高速缓存目录中保留了推测性写入记录。冲突检查作为目录查找的一部分发生。不冲突的推测版本以不同的缓存方式聚合成聚合版本。推测内存访问请求不会转到主内存。

25. 发明申请

US20110219215A1 ATOMICITY: A MULTI-PRONGED APPROACH 审中-公开
标题翻译：原理：多方面的方法
公开(公告)号：US20110219215A1
公开(公告)日：2011-09-08
申请号：US13008546
申请日：2011-01-18
申请人： Matthias A. Blumrich , Dong Chen , Alan Gara , Philip Heidelberger , Martin Ohmarcht , Burkhard Steinmacher-Burow
发明人： Matthias A. Blumrich , Dong Chen , Alan Gara , Philip Heidelberger , Martin Ohmarcht , Burkhard Steinmacher-Burow
IPC分类号： G06F9/30
CPC分类号： G06F9/524 , G06F12/08
摘要： In a multiprocessor system with speculative execution, atomicity can be approached in several fashions. One approach is to have atomic instructions that achieve multiple functions and are guaranteed to complete. Another approach is to have blocks of code that are grouped to succeed or fail together. A system can incorporate more than one such approach. In implementing more than one approach, the system may prioritize one over another. When conflict detection is done through a directory lookup in cache memory, atomic instructions and atomicity related operations may be implemented in a cache data array access pipeline in that cache memory. This implementation may include feedback to the pipeline for implementing multiple functions within an atomic instruction and also for cascading atomic instructions.
摘要翻译：在具有推测性执行的多处理器系统中，可以以几种方式逼近原子性。一种方法是具有实现多种功能并保证完成的原子指令。另一种方法是将代码块分组成一起成功或失败。系统可以包含多种这样的方法。在实施多种方法时，系统可以优先考虑其他方法。当通过高速缓冲存储器中的目录查找完成冲突检测时，原子指令和原子性相关操作可以在该高速缓冲存储器中的高速缓存数据阵列访问流水线中实现。该实现可以包括用于在原子指令内实现多个功能并且还用于级联原子指令的流水线的反馈。

26. 发明申请

US20070204112A1 LOW LATENCY MEMORY ACCESS AND SYNCHRONIZATION 失效
标题翻译：低延迟存储器访问和同步
公开(公告)号：US20070204112A1
公开(公告)日：2007-08-30
申请号：US11617276
申请日：2006-12-28
申请人： Matthias Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Burkhard Steinmacher-Burow , Todd Takken , Pavlos Vranas
发明人： Matthias Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Burkhard Steinmacher-Burow , Todd Takken , Pavlos Vranas
IPC分类号： G06F12/14
CPC分类号： G06F12/0862 , G06F9/52 , G06F2212/6028
摘要： A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.
摘要翻译：与弱有序的多处理器系统相关联地提供低延迟存储器系统访问。多处理器中的每个处理器共享资源，并且每个共享资源在锁定设备内具有关联的锁，其提供对多处理器中的多个处理器之间的同步的支持以及资源的有序共享。当处理器拥有与该资源相关联的锁定时，处理器仅具有访问资源的权限，并且处理器拥有锁的尝试仅需要单个加载操作，而不是传统的原子负载后跟存储，使得处理器只执行读取操作，并且硬件锁定装置执行后续的写入操作而不是处理器。还公开了用于非连续数据结构的简单预取。重新定义存储器线，使得除了正常的物理存储器数据之外，每行包括足够大的指针以指向存储器中的任何其他行，其中指针用于确定要预取的存储器行而不是一些其它预测算法。这使得硬件能够有效地预取不连续但重复的存储器访问模式。

27. 发明申请

US20120324142A1 LIST BASED PREFETCH 有权
标题翻译：以列表为前提
公开(公告)号：US20120324142A1
公开(公告)日：2012-12-20
申请号：US13593838
申请日：2012-08-24
申请人： Peter Boyle , Norman Christ , Alan Gara , Changhoan Kim , Robert Mawhinney , Martin Ohmacht , Krishnan Sugavanam
发明人： Peter Boyle , Norman Christ , Alan Gara , Changhoan Kim , Robert Mawhinney , Martin Ohmacht , Krishnan Sugavanam
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862
摘要： A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current cache miss address is valid. If the current cache miss address is valid, the list prefetch engine compares the current cache miss address and a list address. A list address represents an address in a list. A list describes an arbitrary sequence of prior cache miss addresses. The prefetch engine prefetches data according to the list, if there is a match between the current cache miss address and the list address.
摘要翻译：列表预取引擎提高并行计算系统的性能。列表预取引擎接收当前高速缓存未命中地址。列表预取引擎评估当前缓存未命中地址是否有效。如果当前高速缓存未命中地址有效，则列表预取引擎将比较当前高速缓存未命中地址和列表地址。列表地址表示列表中的地址。列表描述了先前高速缓存未命中地址的任意序列。如果当前缓存未命中地址和列表地址之间存在匹配，则预取引擎将根据列表预取数据。

28. 发明申请

US20120185672A1 LOCAL-ONLY SYNCHRONIZING OPERATIONS 审中-公开
标题翻译：本地同步操作
公开(公告)号：US20120185672A1
公开(公告)日：2012-07-19
申请号：US13008498
申请日：2011-01-18
申请人： Alan Gara , Martin Ohmacht , Burkhard Steinmacher-Burow , Robert W. Wisniewski
发明人： Alan Gara , Martin Ohmacht , Burkhard Steinmacher-Burow , Robert W. Wisniewski
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/526 , G06F12/0815 , G06F2209/521
摘要： Performing a series of successive synchronizing operations by a core on data shared by a plurality of cores may include a first core indicating an upcoming synchronizing operation on shared data. A second memory layer stores the shared data and tracks the first core's ownership of the shared data. The second memory layer is shared via coherency operations among the first core and one or more second cores. The first core may perform one or more synchronization operations on the shared data without requiring interaction from the second memory layer.
摘要翻译：通过核心对由多个核心共享的数据执行一系列连续同步操作可以包括指示即将到来的对共享数据的同步操作的第一核心。第二存储器层存储共享数据并跟踪第一核心对共享数据的所有权。通过第一核心和一个或多个第二核心之间的一致性操作来共享第二存储器层。第一核可以对共享数据执行一个或多个同步操作，而不需要来自第二存储器层的交互。

29. 发明授权

US08806141B2 List based prefetch 有权
标题翻译：基于列表的预取
公开(公告)号：US08806141B2
公开(公告)日：2014-08-12
申请号：US13593838
申请日：2012-08-24
申请人： Peter Boyle , Norman Christ , Alan Gara , Changhoan Kim , Robert Mawhinney , Martin Ohmacht , Krishnan Sugavanam
发明人： Peter Boyle , Norman Christ , Alan Gara , Changhoan Kim , Robert Mawhinney , Martin Ohmacht , Krishnan Sugavanam
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862
摘要： A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current cache miss address is valid. If the current cache miss address is valid, the list prefetch engine compares the current cache miss address and a list address. A list address represents an address in a list. A list describes an arbitrary sequence of prior cache miss addresses. The prefetch engine prefetches data according to the list, if there is a match between the current cache miss address and the list address.
摘要翻译：列表预取引擎提高并行计算系统的性能。列表预取引擎接收当前高速缓存未命中地址。列表预取引擎评估当前缓存未命中地址是否有效。如果当前高速缓存未命中地址有效，则列表预取引擎将比较当前高速缓存未命中地址和列表地址。列表地址表示列表中的地址。列表描述了先前高速缓存未命中地址的任意序列。如果当前缓存未命中地址和列表地址之间存在匹配，则预取引擎将根据列表预取数据。

30. 发明申请

US20110173397A1 PROGRAMMABLE STREAM PREFETCH WITH RESOURCE OPTIMIZATION 失效
标题翻译：可编程流程资源优化
公开(公告)号：US20110173397A1
公开(公告)日：2011-07-14
申请号：US12684693
申请日：2010-01-08
申请人： Peter Boyle , Norman Christ , Alan Gara , Robert Mawhinney , Martin Ohmacht , Krishnan Sugavanam
发明人： Peter Boyle , Norman Christ , Alan Gara , Robert Mawhinney , Martin Ohmacht , Krishnan Sugavanam
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A stream prefetch engine performs data retrieval in a parallel computing system. The engine receives a load request from at least one processor. The engine evaluates whether a first memory address requested in the load request is present and valid in a table. The engine checks whether there exists valid data corresponding to the first memory address in an array if the first memory address is present and valid in the table. The engine increments a prefetching depth of a first stream that the first memory address belongs to and fetching a cache line associated with the first memory address from the at least one cache memory device if there is not yet valid data corresponding to the first memory address in the array. The engine determines whether prefetching of additional data is needed for the first stream within its prefetching depth. The engine prefetches the additional data if the prefetching is needed.
摘要翻译：流预取引擎在并行计算系统中执行数据检索。引擎从至少一个处理器接收加载请求。引擎评估在加载请求中请求的第一个内存地址是否存在，并且在表中有效。如果第一个存储器地址在表中存在且有效，引擎将检查是否存在与数组中的第一个存储器地址对应的有效数据。如果还没有对应于第一存储器地址的有效数据，则引擎增加第一存储器地址所属的第一流的预取深度并从至少一个高速缓冲存储器设备获取与第一存储器地址相关联的高速缓存行阵列。该引擎确定在其预取深度内的第一个流是否需要预取附加数据。如果需要预取，引擎将预取附加数据。

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