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21. 发明申请

WO2013043602A2 HIGH ENDURANCE NON-VOLATILE STORAGE 审中-公开
标题翻译：高耐久性非挥发性储存
公开(公告)号：WO2013043602A2
公开(公告)日：2013-03-28
申请号：PCT/US2012/055919
申请日：2012-09-18
申请人： SANDISK TECHNOLOGIES, INC. , CHEN, Jian , GOROBETS, Sergei , SPROUSE, Steven , KUO, Tien-chien , LI, Yan , LEE, Seungpil , MAK, Alex , DUTTA, Deepanshu , HIGASHITANI, Masaaki
发明人： CHEN, Jian , GOROBETS, Sergei , SPROUSE, Steven , KUO, Tien-chien , LI, Yan , LEE, Seungpil , MAK, Alex , DUTTA, Deepanshu , HIGASHITANI, Masaaki
IPC分类号： G11C16/10 , G11C11/56 , G11C5/06
CPC分类号： G11C16/10 , G11C5/063 , G11C11/5628 , G11C2211/5641
摘要： A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.
摘要翻译：公开了一种非易失性存储系统，其包括设计用于高耐久性和比其他非易失性存储器单元更低保持性的非易失性存储器单元。

22. 发明申请

WO2012122188A1 NON-VOLATILE STORAGE ELEMENT COMPRISING A FLOATING GATE WITH A PN JUNCTION AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：包含具有PN结的浮动门的非易失性存储元件及其形成方法
公开(公告)号：WO2012122188A1
公开(公告)日：2012-09-13
申请号：PCT/US2012/027920
申请日：2012-03-06
申请人： SANDISK TECHNOLOGIES, INC. , DUNGA, Mohan , LEE, Sanghyun , HIGASHITANI, Masaaki , PHAM, Tuan
发明人： DUNGA, Mohan , LEE, Sanghyun , HIGASHITANI, Masaaki , PHAM, Tuan
IPC分类号： H01L21/28 , H01L21/8247 , H01L29/788 , H01L27/115 , G11C16/04 , H01L29/423 , H01L21/8234
CPC分类号： H01L29/66825 , G11C11/5642 , G11C16/0408 , G11C16/3418 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L29/7881
摘要： Non-volatile storage elements having a PN floating gate (811) are disclosed herein. The floating gate has a P- region (804) near the tunnel oxide (805), and may have an N+ region (808) near the control gate (812). In some embodiments, a P- region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P- region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.
摘要翻译：本文公开了具有PN浮动栅极（811）的非易失性存储元件。浮动栅极具有在隧道氧化物（805）附近的P-区域（804），并且可以在控制栅极（812）附近具有N +区域（808）。在一些实施例中，隧道氧化物附近的P-区域有助于提供良好的数据保持。在一些实施例中，控制栅极附近的N +区域有助于实现控制栅极和浮置栅极之间良好的耦合比。因此，非易失性存储元件的编程是有效的。也可以有效地擦除非易失性存储元件。在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

23. 发明申请

WO2010033409A1 DATA STATE-BASED TEMPERATURE COMPENSATION DURING SENSING IN NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中感测期间基于数据状态的温度补偿
公开(公告)号：WO2010033409A1
公开(公告)日：2010-03-25
申请号：PCT/US2009/056405
申请日：2009-09-09
申请人： SANDISK CORPORATION , DUNGA, Mohan, V. , HIGASHITANI, Masaaki
发明人： DUNGA, Mohan, V. , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/26
CPC分类号： G11C11/5642 , G11C7/04 , G11C16/26
摘要： Temperature effects in a non-volatile storage device are addressed by providing a data state-dependent, and optionally temperature dependent, sense current during verify and read operations. A different sense current (1) is provided for each data state (2), so that a common temperature coefficient (3) is realized for storage elements with different data states. The temperature coefficient for higher states can be reduced to that of lower states. During sensing, a sense time can be adjusted to achieve a desired sense current when a selected storage element is in a conductive state. A fixed voltage trip point may be maintained. During the sense time, a pre-charged capacitor discharges into a selected storage element such as via a bit line and NAND string, when the selected storage element is in a conductive state. The discharge level is translated to a current which is compared to a state-dependent, and optionally temperature dependent, reference current.
摘要翻译：通过在验证和读取操作期间提供数据状态相关的和可选的与温度相关的感测电流来解决非易失性存储设备中的温度效应。为每个数据状态（2）提供不同的感测电流（1），使得对于具有不同数据状态的存储元件实现共同的温度系数（3）。较高状态的温度系数可以降低到较低的状态。在感测期间，当所选择的存储元件处于导通状态时，可以调整感测时间以实现期望的感测电流。可以保持固定的电压跳变点。在感测时间期间，当所选存储元件处于导通状态时，预充电电容器通过位线和NAND串放电到选定的存储元件中。将放电电平转换为与状态相关的，并且可选地与温度相关的参考电流进行比较的电流。

24. 发明申请

WO2009123843A1 NON-VOLATILE STORAGE HAVING A CONNECTED SOURCE AND WELL 审中-公开
标题翻译：具有连接源和非易失性存储的非易失性存储
公开(公告)号：WO2009123843A1
公开(公告)日：2009-10-08
申请号：PCT/US2009/037049
申请日：2009-03-13
申请人： SANDISK CORPORATION , HIGASHITANI, Masaaki
发明人： HIGASHITANI, Masaaki
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/74
CPC分类号： H01L29/66825 , H01L21/743 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well.
摘要翻译：公开了一种非易失性存储装置，其包括形成在阱上的一组连接的非易失性存储元件，位于阱中的位线触点，位于阱中的源极线接触件，连接到该阱的位线位线接触，以及连接到源极线接触点和阱的源极线。

25. 发明申请

WO2008048812A1 FABRICATING NON-VOLATILE MEMORY WITH DUAL VOLTAGE SELECT GATE STRUCTURE 审中-公开
标题翻译：用双电压门控结构制造非易失性存储器
公开(公告)号：WO2008048812A1
公开(公告)日：2008-04-24
申请号：PCT/US2007/080745
申请日：2007-10-08
申请人： SANDISK CORPORATION , MOKHLESI, Nima , HIGASHITANI, Masaaki
发明人： MOKHLESI, Nima , HIGASHITANI, Masaaki
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , G11C16/04
CPC分类号： H01L21/28273 , G11C11/5628 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A select gate structure for a non-volatile storage system include a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an adjacent unselected non-volatile storage element. In particular, an elevated voltage can be applied to the coupling electrode when the adjacent word line is used for programming. A reduced voltage is applied when a non-adjacent word line is used for programming. The voltage can also be set based on other programming criterion. The select gate is provided by a first conductive region while the coupling electrode is provided by a second conductive region formed over, and isolated from, the first conductive region.
摘要翻译：用于非易失性存储系统的选择栅极结构包括独立驱动的选择栅极和耦合电极。耦合电极与NAND串中的字线相邻，并且具有施加的电压，其减小相邻未选择的非易失性存储元件的栅极引起的漏极降低（GIDL）编程干扰。特别地，当相邻字线用于编程时，可以将高电压施加到耦合电极。当使用非相邻字线进行编程时，施加降低的电压。电压也可以根据其他编程标准设定。选择栅极由第一导电区域提供，而耦合电极由形成在第一导电区域上并与之隔离的第二导电区域提供。

26. 发明申请

WO2007081642A2 FLASH DEVICES WITH SHARED WORD LINES 审中-公开
标题翻译：具有共享字线的闪存设备
公开(公告)号：WO2007081642A2
公开(公告)日：2007-07-19
申请号：PCT/US2006/062188
申请日：2006-12-15
申请人： SANDISK CORPORATION , HIGASHITANI, Masaaki
发明人： HIGASHITANI, Masaaki
CPC分类号： G11C16/0483 , G11C8/14 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that peripheral circuits are shared. Separate erase blocks are established by shield plates.
摘要翻译： NAND闪速存储器阵列的字线由同心的矩形形状的闭环形成，其具有大约是所使用的图案化工艺的最小特征尺寸的一半的宽度。所得到的电路具有连接在一起的字线，使得外围电路被共享。单独的擦除块由屏蔽板建立。

27. 发明申请

WO2006069184A1 EEPROM ARRAY WITH SELF-ALIGNED SHALLOW-TRENCH ISOLATION 审中-公开
标题翻译：具有自对准SHELLOW-TRENCH隔离的EEPROM阵列
公开(公告)号：WO2006069184A1
公开(公告)日：2006-06-29
申请号：PCT/US2005/046448
申请日：2005-12-19
申请人： SANDISK CORPORATION , PHAM, Tuan , HIGASHITANI, Masaaki
发明人： PHAM, Tuan , HIGASHITANI, Masaaki
IPC分类号： H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A method of making a memory array and peripheral circuits together on a single substrate forms a dielectric layer (302), floating gate layer (306), inter-layer dielectric (308) and mask layer (310) across all regions of the substrate. After self-aligned shallow-trench isolation structures (STI) have been formed, these layers are removed from the peripheral regions and dielectrics (640, 860) of different thicknesses are formed in the peripheral regions according to the voltages of the circuits in these regions. A conductive layer (970) is formed over the memory array and the peripheral circuits to form control gates in the memory array and form gate electrodes in the peripheral regions.
摘要翻译：将存储器阵列和外围电路一起制成在单个衬底上的方法在衬底的所有区域上形成介电层（302），浮动栅层（306），层间电介质（308）和掩模层（310）。在形成自对准的浅沟槽隔离结构（STI）之后，这些层从周边区域移除，并且根据这些区域中的电路的电压在外围区域中形成不同厚度的电介质（640,860）。在存储器阵列和外围电路上形成导电层（970），以在存储器阵列中形成控制栅极，并在外围区域中形成栅电极。

28. 发明申请

WO2011011525A1 METHOD OF FORMING NANOSTRUCTURE-BASED NAND FLASH CELLS AND THE PERIPHERY CIRCUITS THEREOF 审中-公开
标题翻译：形成基于纳米结构的NAND闪存细胞及其周围电路的方法
公开(公告)号：WO2011011525A1
公开(公告)日：2011-01-27
申请号：PCT/US2010/042766
申请日：2010-07-21
申请人： SANDISK CORPORATION , PURAYATH, Vinod, Robert , KAI, James, K. , HIGASHITANI, Masaaki , ORIMOTO, Takashi , MATAMIS, George , CHIEN, Henry
发明人： PURAYATH, Vinod, Robert , KAI, James, K. , HIGASHITANI, Masaaki , ORIMOTO, Takashi , MATAMIS, George , CHIEN, Henry
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115
CPC分类号： H01L21/76224 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L27/11573 , H01L29/788 , Y10S438/962 , Y10S977/774 , Y10S977/936
摘要： Nanostructure-based charge storage regions (CSR1-CSR5) are included in non-volatile memory devices and integrated with the fabrication of select gates (SGl) and peripheral circuitry (PGl, PG2) One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.
摘要翻译：基于纳米结构的电荷存储区域（CSR1-CSR5）被包括在非易失性存储器件中，并与选择栅极（SG1）和外围电路（PG1，PG2）的制造集成在一个衬底上施加一个或多个纳米结构涂层存储器阵列区域和外围电路区域。提供了用于从衬底的不需要的区域（例如选择栅极和外围晶体管的目标区域）去除纳米结构涂层的各种工艺。在一个实例中，使用基于自组装的工艺来形成一个或多个纳米结构涂层以在衬底的有源区上选择性地形成纳米结构。自组装允许形成彼此电隔离的纳米结构的离散线，而不需要对纳米结构涂层进行图案化或蚀刻。

29. 发明申请

WO2008122012A2 INTEGRATED NON-VOLATILE MEMORY AND PERIPHERAL CIRCUITRY FABRICATION 审中-公开
标题翻译：集成的非易失性存储器和外围电路制造
公开(公告)号：WO2008122012A2
公开(公告)日：2008-10-09
申请号：PCT/US2008/059035
申请日：2008-04-01
申请人： SANDISK CORPORATION , KAI, James , PHAM, Tuan , HIGASHITANI, Masaaki , MATAMIS, George , ORIMOTO, Takashi
发明人： KAI, James , PHAM, Tuan , HIGASHITANI, Masaaki , MATAMIS, George , ORIMOTO, Takashi
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11536 , H01L27/11539
摘要： Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.
摘要翻译：提供非易失性存储器和集成存储器和外围电路制造工艺。使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。中间电介质层设置在电荷存储区域的上方。将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

30. 发明申请

WO2008048813A1 NON-VOLATILE MEMORY WITH DUAL VOLTAGE SELECT GATE STRUCTURE 审中-公开
标题翻译：具有双电压选择门结构的非易失性存储器
公开(公告)号：WO2008048813A1
公开(公告)日：2008-04-24
申请号：PCT/US2007/080746
申请日：2007-10-08
申请人： SANDISK CORPORATION , MOKHLESI, Nima , HIGASHITANI, Masaaki
发明人： MOKHLESI, Nima , HIGASHITANI, Masaaki
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , G11C16/04
CPC分类号： H01L21/28273 , G11C11/5628 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A select gate structure (1260) for a non-volatile storage system includes a select gate (1022) and a coupling electrode (1023) which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage (Vces) applied which reduces gate induced drain lowering (GIDL) program disturb of an adjacent unselected non-volatile storage element. In particular, an elevated voltage can be applied to the coupling electrode when the adjacent word line is used for programming. A reduced voltage is applied when a non-adjacent word line is used for programming. The voltage can also be set based on other programming criteria. The select gate is provided by a first conductive region (1230) while the coupling electrode is provided by a second conductive region formed over, and isolated from, the first conductive region.
摘要翻译：用于非易失性存储系统的选择栅极结构（1260）包括独立驱动的选择栅极（1022）和耦合电极（1023）。耦合电极与NAND串中的字线相邻，并且具有施加的电压（Vces），其减小相邻未选择的非易失性存储元件的栅极引起的漏极降低（GIDL）编程干扰。特别地，当相邻字线用于编程时，可以将高电压施加到耦合电极。当使用非相邻字线进行编程时，施加降低的电压。也可以根据其他编程标准设定电压。选择栅极由第一导电区域（1230）提供，而耦合电极由形成在第一导电区域上并与之隔离的第二导电区域提供。

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