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21. 发明公开

EP2301033A1 IMPROVED PROGRAMMING ALGORITHM TO REDUCE DISTURB WITH MINIMAL EXTRA TIME PENALTY 有权转让
标题翻译：改进的项目算法的干扰缓解与很少的额外时间损失
公开(公告)号：EP2301033A1
公开(公告)日：2011-03-30
申请号：EP09770884.6
申请日：2009-06-23
申请人： Sandisk Corporation
发明人： LEE, Dana , DUTTA, Deepanshu , DONG, Yingda
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.

22. 发明授权

EP2301033B1 IMPROVED PROGRAMMING ALGORITHM TO REDUCE DISTURB WITH MINIMAL EXTRA TIME PENALTY 有权转让
标题翻译：改进的编程算法，以最小的额外时间处罚来减少干扰
公开(公告)号：EP2301033B1
公开(公告)日：2011-11-30
申请号：EP09770884.6
申请日：2009-06-23
申请人： Sandisk Corporation
发明人： LEE, Dana , DUTTA, Deepanshu , DONG, Yingda
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.
摘要翻译：在多程序编程过程中，编程时间在非易失性存储器中减少。在第一次编程过程中，高状态单元通过一系列编程脉冲来编程，以识别快速和慢速高状态单元，而较低状态单元被锁定编程。一旦识别，快速高状态单元暂时被锁定编程，而慢速高状态单元继续被编程为其最终预期状态。此外，编程脉冲急剧增加以编程慢速高状态单元。在第二遍编程中，快速高状态单元与其他较低状态单元一起编程，直到它们全部达到它们各自的预期状态。与其中所有高状态单元在第一遍编程中被编程的方法相比，节省了时间。

23. 发明公开

EP2223304A1 REGULATION OF SOURCE POTENTIAL TO COMBAT CELL SOURCE IR DROP 审中-公开
标题翻译：调整主要潜在成防止电池输出电压降
公开(公告)号：EP2223304A1
公开(公告)日：2010-09-01
申请号：EP08865757.2
申请日：2008-12-12
申请人： Sandisk Corporation
发明人： LEE, Dana , MOKHLESI, Nima , SEKAR, Deepak Chandra
IPC分类号： G11C16/30
CPC分类号： G11C16/30
摘要： Techniques are presented for dealing with possible source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits of a non-volatile memory. The error is caused by a voltage drop across the resistance of the source path to the chip's ground when current flows. For this purpose, the memory device includes a source potential regulation circuit, including an active circuit element having a first input connected to a reference voltage and having a second input connected as a feedback loop that is connectable to the aggregate node from which the memory cells of a structural block have their current run to ground. A variation includes a non-linear resistive element connectable between the aggregate node and ground.

24. 发明公开

EP2102868A2 METHOD AND SYSTEM OF LOW VOLTAGE PROGRAMMING OF NON-VOLATILE MEMORY CELLS 有权转让
标题翻译：方法和系统低电压编程非易失性存储单元
公开(公告)号：EP2102868A2
公开(公告)日：2009-09-23
申请号：EP07865657.6
申请日：2007-12-13
申请人： Sandisk Corporation
发明人： LEE, Dana , LUTZE, Jeffrey
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3454
摘要： A low voltage method and system of programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n-1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).

25. 发明公开

EP2181446A1 REDUCING THE IMPACT OF INTERFERENCE DURING PROGRAMMING 有权
标题翻译：减少编程过程中干扰的影响
公开(公告)号：EP2181446A1
公开(公告)日：2010-05-05
申请号：EP08829629.8
申请日：2008-08-28
申请人： Sandisk Corporation
发明人： LEE, Dana , YERO, Emilio
IPC分类号： G11C16/10 , G11C16/02 , G11C29/00
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5621
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
摘要翻译：提出了一种用于编程非易失性存储器的系统，其减少了来自邻居提升的干扰的影响。存储器单元被分成两个或更多组。在一个例子中，存储器单元被分成奇数和偶数存储器单元; 但是，也可以使用其他分组。在第一次触发之前，第一组存储器单元与第二组存储器单元一起被编程。在第一触发之后并且在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。在第二次触发之后，第一组存储器单元与第二组存储器单元一起被编程。在两次触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

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