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21. 发明授权

US07697318B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07697318B2
公开(公告)日：2010-04-13
申请号：US11964260
申请日：2007-12-26
申请人： Ryo Fukuda , Daisaburo Takashima
发明人： Ryo Fukuda , Daisaburo Takashima
IPC分类号： G11C11/24
CPC分类号： G11C11/405 , G11C5/063 , G11C7/18 , G11C8/14 , G11C11/4097 , H01L27/0207 , H01L27/10897
摘要： A memory cell array includes a plurality of memory cells arranged at intersections of bit line pairs and word lines. Each memory cell includes a first transistor having one main electrode connected to a first bit line, a second transistor having one main electrode connected to a second bit line, a first node electrode for data-storage connected to the other main electrode of the first transistor, a second node electrode for data-storage connected to the other main electrode of the second transistor, and a shield electrode formed surrounding the first and second node electrodes. The first and second transistors have respective gates both connected to an identical word line, and the first and second bit lines are connected to an identical sense amp. The first and second node electrodes, the first and second bit lines, the word line and the shield electrode are isolated from each other using insulating films.
摘要翻译：存储单元阵列包括布置在位线对和字线的交点处的多个存储单元。每个存储单元包括具有连接到第一位线的一个主电极的第一晶体管，具有连接到第二位线的一个主电极的第二晶体管，用于数据存储的第一节点电极连接到第一晶体管的另一个主电极，连接到第二晶体管的另一个主电极的用于数据存储的第二节点电极和围绕第一和第二节点电极形成的屏蔽电极。第一和第二晶体管具有连接到相同字线的相应门，并且第一和第二位线连接到相同的感测放大器。第一和第二节点电极，第一和第二位线，字线和屏蔽电极使用绝缘膜彼此隔离。

22. 发明授权

US07692963B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07692963B2
公开(公告)日：2010-04-06
申请号：US11934337
申请日：2007-11-02
申请人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C11/409 , G11C11/4091 , G11C11/4097 , G11C11/4099 , G11C2211/4016 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.
摘要翻译：本公开涉及包括半导体层的半导体存储器件; 与所述半导体层的第一表面接触的电荷陷阱膜; 与所述半导体层的第二表面接触的栅极绝缘膜，所述第二表面与所述第一表面相对; 与电荷陷阱膜接触的背栅电极; 与栅极绝缘膜接触的栅电极; 在半导体层中形成的源极和漏极; 以及设置在所述漏极和源极之间的体区，所述体区域处于电浮置状态，其中通过改变数量来调整包括所述源极，漏极和所述栅电极的存储单元的阈值电压或漏极电流的多数载体积聚在身体区域中，并且一定量的电荷被捕获到电荷陷阱膜中。

23. 发明授权

US07406637B2 Semiconductor memory device capable of testing memory cells at high speed 有权
标题翻译：能够高速测试存储单元的半导体存储器件
公开(公告)号：US07406637B2
公开(公告)日：2008-07-29
申请号：US11008270
申请日：2004-12-10
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/36 , G11C2029/3602
摘要： A semiconductor memory device comprises a memory core, data control circuit, flag register, data register and computation circuit. The memory core has a plurality of memory cells for storing data. The data control circuit writes and reads first test data to and from the memory cells in synchrony with a clock signal. The flag register stores a plurality of flag data items. The data register stores second test data input corresponding to input of a command. The computation circuit performs, at every cycle, computation of the second test data, stored in the data register, and each of the flag data items stored in the flag register, thereby generating the first test data, until an n-th (n is a positive integer) cycle of the clock signal is reached. The first test data is written to the memory cells by the data control circuit.
摘要翻译：半导体存储器件包括存储器核，数据控制电路，标志寄存器，数据寄存器和计算电路。存储器核具有用于存储数据的多个存储单元。数据控制电路与时钟信号同步地向存储器单元写入和读出第一测试数据。标志寄存器存储多个标志数据项。数据寄存器存储对应于命令输入的第二测试数据输入。计算电路在每个周期执行存储在数据寄存器中的第二测试数据和存储在标志寄存器中的每个标志数据项的计算，从而生成第一测试数据，直到第n（n是时钟信号的正整数）周期。第一测试数据由数据控制电路写入存储单元。

24. 发明授权

US06865126B2 Semiconductor memory device capable of relieving defective cell 失效
标题翻译：能够缓解缺陷电池的半导体存储器件
公开(公告)号：US06865126B2
公开(公告)日：2005-03-08
申请号：US10933517
申请日：2004-09-03
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G11C29/04 , G11C11/401 , G11C11/407 , G11C11/4096 , G11C29/00 , G11C7/00 , G06F12/00 , G11C7/02 , G11C8/00
CPC分类号： G11C29/848 , G11C11/4096 , G11C2207/002
摘要： A semiconductor memory device includes a data line shift circuit, a plurality of data mask lines connected to the plurality of sense amplifier write circuits, respectively, and a plurality of mask circuits. The plurality of mask circuits each include at least one shift switch circuit and supply a mask signal to a sense amplifier write circuit, which is connected to a mask circuit different from that before a data line is shifted by the data line shift circuit, through the shift switch circuit and supply the mask signal to a sense amplifier write circuit, which is connected to the same mask circuit as that before the data line is shifted, not through the shift switch circuit.
摘要翻译：半导体存储器件包括数据线移位电路，分别连接到多个读出放大器写入电路的多个数据屏蔽线以及多个掩模电路。多个屏蔽电路各自包括至少一个移位开关电路，并将掩模信号提供给读出放大器写入电路，读出放大器写入电路连接到不同于数据线被数据线移位电路移位之前的掩模电路，通过移位开关电路，并将掩模信号提供给读出放大器写入电路，该读取电路写入电路连接到与数据线移位之前相同的屏蔽电路，而不是通过移位开关电路。

25. 发明授权

US06804155B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US06804155B2
公开(公告)日：2004-10-12
申请号：US10319591
申请日：2002-12-16
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G11C700
CPC分类号： G11C29/848
摘要： A semiconductor storage device includes an array region, which includes memory cell array blocks and is connected to a (k: k is a natural number)-number of data input/output lines. A (k+m: m is a natural number)-number of common internal data lines are provided in common to the memory cell array blocks. A (k+m+n: n is a natural number)-number of individual internal data lines are provided to each memory cell array block. An individual line connection circuit is configured to respectively connect a (k+m)-number of the (k+m+n)-number of individual internal data lines to the (k+m)-number of common internal data lines, in accordance with a first defect information signal. A common line connection circuit is configured to respectively connect a k-number of the (k+m)-number of common internal data lines to the k-number of data input/output lines, in accordance with a second defect information signal.
摘要翻译：半导体存储装置包括阵列区域，其包括存储单元阵列块，并连接到数据输入/输出线路的（k：k是自然数）个数字。 A（k + m：m是自然数） - 公共内部数据线的数量被公共地提供给存储单元阵列块。 A（k + m + n：n是自然数） - 各个内部数据线的数量被提供给每个存储单元阵列块。单独线路连接电路被配置为分别将（k + m +）个数的（k + m + n）个数的各个内部数据线连接到（k + m）个数字的公共内部数据线，根据第一缺陷信息信号。公共线路连接电路被配置为根据第二缺陷信息信号将k个（k + m）个公共内部数据线的k个数目与k个数据输入/输出线分别连接。

26. 发明授权

US06647520B1 Semiconductor device 有权
标题翻译：测试中的半导体器件具有通过切换信号指定要在外部地址中选择的存储单元阵列块的地址
公开(公告)号：US06647520B1
公开(公告)日：2003-11-11
申请号：US09708064
申请日：2000-11-08
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G11C2900
CPC分类号： G11C29/26 , G11C2029/1802
摘要： A semiconductor device has a least one logic circuit and at least one memory macro cell having a plurality of memory cell array blocks each composed of a plurality of memory cells. Addresses for designating the memory cell array blocks in test are selected among external addresses by a switching signal. The semiconductor device may have a plurality of memory macro cells having a plurality of memory cell array blocks each composed of a plurality of memory cells. The memory macro cells are switched in configuration as having the same length of rows or columns between the memory macro cells in test. The configuration is different from a configuration of row and column for a regular operation.
摘要翻译：半导体器件具有至少一个逻辑电路和至少一个具有由多个存储器单元组成的多个存储单元阵列块的存储器宏单元。通过切换信号在外部地址中选择用于指定测试中的存储单元阵列块的地址。半导体器件可以具有多个存储器宏单元，其具有由多个存储单元组成的多个存储单元阵列块。存储器宏单元被配置为在测试中的存储器宏单元之间具有相同长度的行或列。该配置与常规操作的行和列的配置不同。

27. 发明授权

US06438044B1 Semiconductor memory device and method of testing the same 有权
公开(公告)号：US06438044B1
公开(公告)日：2002-08-20
申请号：US09812681
申请日：2001-03-21
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G11C2900
摘要： Disclosed is a semiconductor memory device comprising a memory circuit including an array of regular memory cells and an array of redundancy memory cells, a memory element including nonvolatile elements for storing unrewritable data that can be stored from outside, a register for holding the data of the memory element before the activation of the memory device, a redundancy determining circuit for comparing the data held in the register and the externally input address and determining the use or non-use of any of the redundancy memory cells and a redundancy data rewriting circuit adapted to receive a redundancy data from a source other than the memory element and input it to the register to use the redundancy data for rewriting.

28. 发明授权

US06275428B1 Memory-embedded semiconductor integrated circuit device and method for testing same 有权
标题翻译：内存式半导体集成电路器件及其测试方法
公开(公告)号：US06275428B1
公开(公告)日：2001-08-14
申请号：US09598209
申请日：2000-06-21
申请人： Ryo Fukuda , Osamu Wada , Shinji Miyano
发明人： Ryo Fukuda , Osamu Wada , Shinji Miyano
IPC分类号： G11C700
CPC分类号： G11C29/14 , G11C29/48 , G11C2207/104
摘要： There is provided a memory-embedded semiconductor integrated circuit device capable of being tested in a shorter test time. The memory-embedded semiconductor integrated circuit device includes: a logic part provided on a semiconductor substrate; a memory macro provided on the semiconductor substrate to be consolidated with the logic part; a test input terminal for inputting a test input signal; a test circuit including a test signal generator for generating an output switching signal and a test signal, which serves to carry out a test operation of the memory macro, on the basis of the test input signal, and a switching circuit for selectively outputting one of an output of the memory macro, which has been test-operated by the test signal, and the test input signal in accordance with the output switching signal; and a test output terminal for receiving an output of the switching circuit to output the output of the switching circuit to the outside.
摘要翻译：提供了一种能够在较短测试时间内测试的内存嵌入式半导体集成电路器件。存储器嵌入式半导体集成电路器件包括：设置在半导体衬底上的逻辑部分; 提供在半导体衬底上以与逻辑部分合并的存储器宏; 用于输入测试输入信号的测试输入端; 测试电路，包括用于产生输出切换信号的测试信号发生器和用于基于测试输入信号执行存储器宏的测试操作的测试信号;以及切换电路，用于选择性地输出已经由测试信号测试的存储器宏的输出和根据输出切换信号的测试输入信号; 以及测试输出端子，用于接收开关电路的输出，以将开关电路的输出输出到外部。

29. 发明授权

US5418750A Semiconductor memory device for suppressing noises occurring on bit and word lines 失效
标题翻译：用于抑制位和字线上发生的噪声的半导体存储器件
公开(公告)号：US5418750A
公开(公告)日：1995-05-23
申请号：US200107
申请日：1994-02-22
申请人： Shinichiro Shiratake , Takehiro Hasegawa , Daisaburo Takashima , Ryu Ogiwara , Ryo Fukuda
发明人： Shinichiro Shiratake , Takehiro Hasegawa , Daisaburo Takashima , Ryu Ogiwara , Ryo Fukuda
IPC分类号： G11C11/407 , G11C11/405 , G11C11/4091 , G11C11/4096 , G11C11/4097 , G11C7/00
CPC分类号： G11C11/4096 , G11C11/4091 , G11C11/4097
摘要： A semiconductor memory device includes a series of memory cells, a series of bit lines respectively connected to the memory cells, a series of sense amplifiers, connected to corresponding bit line groups including predetermined number of bit lines of the series of bit lines, for reading out data of memory cells connected to bit lines of the bit line group, the bit line groups including at least adjacent first and second bit line groups, at least first and second transistors allocated between the bit lines and the sense amplifiers and having gates, for selectively connecting the bit lines and the sense amplifiers, and a series of control signal lines commonly connected to the first transistors connected to the first bit line groups and the second transistors connected to the second bit line groups, such that the first transistors connected to the first bit line groups are regularly arranged in one direction, and second transistors connected to the second bit line groups adjacent to the first bit line groups are regularly arranged in an opposite direction.
摘要翻译：半导体存储器件包括一系列存储器单元，分别连接到存储器单元的一系列位线，一系列读出放大器，连接到包括一系列位线的预定数量位线的相应位线组，用于读取连接到位线组的位线的存储器单元的输出数据，位线组包括至少相邻的第一和第二位线组，分配在位线和读出放大器之间并具有门的至少第一和第二晶体管，用于选择性地连接位线和读出放大器，以及一系列控制信号线，共同连接到连接到第一位线组的第一晶体管和连接到第二位线组的第二晶体管，使得连接到第一位线组的第一晶体管第一位线组在一个方向上规则地排列，第二晶体管连接到第二位线组第一位线组以相反的方向规则地布置。

30. 发明授权

US08258817B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08258817B2
公开(公告)日：2012-09-04
申请号：US12884623
申请日：2010-09-17
申请人： Ryo Fukuda , Masaru Koyanagi
发明人： Ryo Fukuda , Masaru Koyanagi
IPC分类号： H03K5/153
CPC分类号： H01L27/092 , H01L2924/0002 , H03F3/3028 , H03F3/45183 , H03F2200/411 , H03F2203/45511 , H01L2924/00
摘要： According to one embodiment, a semiconductor integrated circuit includes first to six transistors and a constant current source circuit. The first and second transistors form a current mirror circuit connected to a first power source node. The third and fourth transistors form a differential pair circuit. The third and fourth transistors receive first and second external signals at their gates, respectively. The constant current source circuit has one end connected to source terminals of the third and fourth transistors, and the other end connected to a second power source node. The fifth and sixth transistors form a current pathway between a common gate node of the first and second transistors and the constant current source circuit. The gate of fifth transistor is connected to a signal output node. The gate of sixth transistor receives a signal of logic opposite to a signal to be obtained at the signal output node.
摘要翻译：根据一个实施例，半导体集成电路包括第一至六个晶体管和恒流源电路。第一和第二晶体管形成连接到第一电源节点的电流镜电路。第三和第四晶体管形成差分对电路。第三和第四晶体管分别在其栅极处接收第一和第二外部信号。恒流源电路的一端连接到第三和第四晶体管的源极端子，另一端连接到第二电源节点。第五和第六晶体管在第一和第二晶体管的公共栅极节点与恒流源电路之间形成电流通路。第五晶体管的栅极连接到信号输出节点。第六晶体管的栅极接收与在信号输出节点处获得的信号相反的逻辑信号。

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