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21. 发明申请

US20130265734A1 INTERCHIP COMMUNICATION USING EMBEDDED DIELECTRIC AND METAL WAVEGUIDES 审中-公开
标题翻译：使用嵌入式电介质和金属波导的交互通信
公开(公告)号：US20130265734A1
公开(公告)日：2013-10-10
申请号：US13439646
申请日：2012-04-04
申请人： Juan A. Herbsommer , Robert F. Payne , Marco Corsi , Baher S. Haroun , Hassan Ali
发明人： Juan A. Herbsommer , Robert F. Payne , Marco Corsi , Baher S. Haroun , Hassan Ali
IPC分类号： H05K1/14 , H05K1/11
CPC分类号： G02B6/12004 , G02B6/1228 , G02B6/43 , H01L2223/6627 , H01L2224/16227 , H01L2924/15311 , H01P3/121 , H01P3/122 , H01P5/107 , H05K1/0239 , H05K1/0243 , H05K1/025 , H05K1/0274 , H05K2201/0187 , H05K2201/037 , H05K2201/09618 , H05K2201/10098
摘要： An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.
摘要翻译：提供了一种装置。存在具有封装基板和集成电路（IC）的电路组件。封装衬底具有微带线，并且IC被固定到封装衬底并且电耦合到微带线。电路板也固定到封装衬底。介质波导固定在电路板上。电介质波导具有延伸到位于电介质波导和微带线之间的过渡区域的介质芯，并且微带线被配置为与介质波导形成通信链路。

22. 发明申请

US20130147520A1 COMPARATOR WITH IMPROVED TIME CONSTANT 有权
标题翻译：具有改进时间的比较器
公开(公告)号：US20130147520A1
公开(公告)日：2013-06-13
申请号：US13323540
申请日：2011-12-12
申请人： Robert F. Payne
发明人： Robert F. Payne
IPC分类号： H03K5/00
CPC分类号： H03K5/249 , H03K5/2481
摘要： An apparatus for comparing differential input signal inputs is provided. The apparatus comprises a CMOS sense amplifier (which has having a first input terminal, a second input terminal, a first output terminal, and a second output terminal), a first output circuit (which has a first load capacitance), a second output circuit (which has a second load capacitance), and an isolation circuit. The isolation circuit is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier. The isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier.
摘要翻译：提供了一种用于比较差分输入信号输入的装置。该装置包括CMOS读出放大器（其具有第一输入端，第二输入端，第一输出端和第二输出端），第一输出电路（其具有第一负载电容），第二输出电路（其具有第二负载电容）和隔离电路。隔离电路耦合在CMOS读出放大器的第一输出端与第一输出电路之间，耦合在CMOS读出放大器的第二输出端和CMOS读出放大器的第二输出端之间。隔离电路将第一和第二负载电容与CMOS读出放大器隔离。

23. 发明申请

US20130021188A1 MULTIPLEXED AMPLIFIER WITH REDUCED GLITCHING 审中-公开
标题翻译：多功能放大器，具有降低玻璃化
公开(公告)号：US20130021188A1
公开(公告)日：2013-01-24
申请号：US13554972
申请日：2012-07-20
申请人： Robert F. Payne
发明人： Robert F. Payne
IPC分类号： H03M1/34
CPC分类号： H03M1/0872 , H03M1/1215 , H03M1/1225 , H03M1/164 , H03M1/44
摘要： In many applications, which use amplifiers that operate at less than 50% duty cycle, it would be advantageous to reduce the number amplifiers to reduce power consumption. Here, an amplifier is provided which is time multiplexed to accommodate multiple data paths. Additionally, reset circuitry or a reset mechanism is provided at the output terminals of this amplifier to briefly short the output terminals to generally prevent glitching that may result from switching between data paths.
摘要翻译：在使用以小于50％工作周期工作的放大器的许多应用中，减少数量放大器以降低功耗将是有利的。这里，提供了一种放大器，其被时分复用以容纳多个数据路径。此外，在该放大器的输出端子处提供复位电路或复位机构，以短暂地输出端子短路，以防止可能由数据路径之间切换引起的毛刺。

24. 发明授权

US08305114B2 Track-and-hold circuit with low distortion 有权
标题翻译：具有低失真的跟踪保持电路
公开(公告)号：US08305114B2
公开(公告)日：2012-11-06
申请号：US12862455
申请日：2010-08-24
申请人： Marco Corsi , Robert F. Payne
发明人： Marco Corsi , Robert F. Payne
IPC分类号： H03K5/00
CPC分类号： G11C27/026 , H03M1/0624 , H03M1/1245
摘要： A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit. The RC network receives the analog input signal and is scaled to change the location of a zero to reduce the signal-dependence of the sampling instant.
摘要翻译：提供跟踪和保持电路。该跟踪和保持电路适于跟踪模拟输入信号并且在采样时刻保持模拟输入信号的采样电压，以响应于与保持信号交替的轨道信号由其它电路进行处理。优选地，跟踪和保持电路包括双向电流源，其通过第一输出节点和第二输出节点来源和吸收电流，单位增益放大器耦合到双向的第一和第二输出节点电流源，并且接收模拟输入信号，耦合到单位增益放大器的输出的电阻器和耦合在电阻器和地之间的电容器。然而，感兴趣的是双向电流源，其包括适于接收轨道信号和保持信号并且耦合到第一和第二输出节点的差分输入电路以及耦合到差分输入电路。 RC网络接收模拟输入信号，并被缩放以改变零点的位置以减小采样时刻的信号依赖性。

25. 发明授权

US08248289B2 Power and area efficient interleaved ADC 有权
标题翻译：电源和区域高效交错ADC
公开(公告)号：US08248289B2
公开(公告)日：2012-08-21
申请号：US12868539
申请日：2010-08-25
申请人： William J. Bright , Robert F. Payne
发明人： William J. Bright , Robert F. Payne
IPC分类号： H03M1/34
CPC分类号： H03M1/1215 , H03M1/1225 , H03M1/164 , H03M1/44
摘要： Pipeline analog-to-digital converters (ADCs) are commonly used for high frequency applications; however, operating at high sampling rates will often result in high power consumption or tight timing constraints. Here, though, an ADC is provided that allows for relaxed timing (which enables a high sampling rate) with low power consumption. This is accomplished through the use of multiplexed, front-end track-and-hold (T/H) circuits that sample on non-overlapping portions of a clocking signal in conjunction with “re-used” or shared analog processing circuitry.
摘要翻译：管道模数转换器（ADC）通常用于高频应用; 然而，以高采样率运行通常会导致高功耗或严格的时序限制。然而，在这里，提供了一种ADC，其具有低功耗的轻松定时（其实现高采样率）。这通过使用多路复用的前端跟踪保持（T / H）电路来实现，该电路在“重用”或共享的模拟处理电路的同时在时钟信号的非重叠部分上进行采样。

26. 发明申请

US20110043257A1 TRACK-AND-HOLD CIRCUIT WITH LOW DISTORTION 有权
标题翻译：具有低失真的跟踪和保持电路
公开(公告)号：US20110043257A1
公开(公告)日：2011-02-24
申请号：US12862455
申请日：2010-08-24
申请人： Marco Corsi , Robert F. Payne
发明人： Marco Corsi , Robert F. Payne
IPC分类号： H03K5/00
CPC分类号： G11C27/026 , H03M1/0624 , H03M1/1245
摘要： A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit. The RC network receives the analog input signal and is scaled to change the location of a zero to reduce the signal-dependence of the sampling instant.
摘要翻译：提供跟踪和保持电路。该跟踪和保持电路适于跟踪模拟输入信号并且在采样时刻保持模拟输入信号的采样电压，以响应于与保持信号交替的轨道信号由其它电路进行处理。优选地，跟踪和保持电路包括双向电流源，其通过第一输出节点和第二输出节点来源和吸收电流，单位增益放大器耦合到双向的第一和第二输出节点电流源，并且接收模拟输入信号，耦合到单位增益放大器的输出的电阻器和耦合在电阻器和地之间的电容器。然而，感兴趣的是双向电流源，其包括适于接收轨道信号和保持信号并且耦合到第一和第二输出节点的差分输入电路以及耦合到差分输入电路。 RC网络接收模拟输入信号，并被缩放以改变零点的位置以减小采样时刻的信号依赖性。

27. 发明授权

US07804337B2 Method and apparatus of SFDR enhancement 有权
标题翻译： SFDR增强的方法和装置
公开(公告)号：US07804337B2
公开(公告)日：2010-09-28
申请号：US12393182
申请日：2009-02-26
申请人： Robert F. Payne , Marco Corsi
发明人： Robert F. Payne , Marco Corsi
IPC分类号： H03K5/00
CPC分类号： H03M1/0836 , G11C27/026 , H03M1/0682 , H03M1/069 , H03M1/1245 , H03M1/164
摘要： A track-and-hold or sample-and-hold (S/H) circuit for an analog-to-digital converter (ADC) is provided. A difference between the disclosed S/H circuit and conventional S/H circuits is the use of a peaking circuit. This peaking circuit generally provides increased current to switching transistor when transitioning between track and hold which can increase the Spurious-Free Dynamic Range (SFDR) as low frequencies, by as much as 15dB.
摘要翻译：提供了用于模数转换器（ADC）的跟踪保持或采样保持（S / H）电路。所公开的S / H电路和常规S / H电路之间的区别在于使用峰值电路。该峰值电路通常在轨道和保持之间转换时向开关晶体管提供增加的电流，这可以将无杂散动态范围（SFDR）降低多达15dB。

28. 发明授权

US07804336B2 Track-and-hold circuit with low distortion 有权
标题翻译：具有低失真的跟踪保持电路
公开(公告)号：US07804336B2
公开(公告)日：2010-09-28
申请号：US12393164
申请日：2009-02-26
申请人： Marco Corsi , Robert F. Payne
发明人： Marco Corsi , Robert F. Payne
IPC分类号： H03K5/00
CPC分类号： G11C27/026 , H03M1/0624 , H03M1/1245
摘要： A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit. The RC network receives the analog input signal and is scaled to change the location of a zero to reduce the signal-dependence of the sampling instant.
摘要翻译：提供跟踪和保持电路。该跟踪和保持电路适于跟踪模拟输入信号并且在采样时刻保持模拟输入信号的采样电压，以响应于与保持信号交替的轨道信号由其它电路进行处理。优选地，跟踪和保持电路包括双向电流源，其通过第一输出节点和第二输出节点来源和吸收电流，单位增益放大器耦合到双向的第一和第二输出节点电流源，并且接收模拟输入信号，耦合到单位增益放大器的输出的电阻器和耦合在电阻器和地之间的电容器。然而，感兴趣的是双向电流源，其包括适于接收轨道信号和保持信号并且耦合到第一和第二输出节点的差分输入电路以及耦合到差分输入电路。 RC网络接收模拟输入信号，并被缩放以改变零点的位置以减小采样时刻的信号依赖性。

29. 发明授权

US07782932B2 Circuit and method for evaluating the performance of an adaptive decision feedback equalizer-based serializer deserializer and serdes incorporating the same 有权
标题翻译：用于评估基于自适应判决反馈均衡器的串行器解串器和包含其的串行器的性能的电路和方法
公开(公告)号：US07782932B2
公开(公告)日：2010-08-24
申请号：US10831502
申请日：2004-04-23
申请人： Robert F. Payne , Bhavesh G. Bhakta
发明人： Robert F. Payne , Bhavesh G. Bhakta
IPC分类号： H04Q1/20 , H04B3/46 , H04B17/00
CPC分类号： G01R31/31715 , H04L25/03057
摘要： A circuit and method for evaluating serializer deserializer (SERDES) performance that is particularly advantageous when the SERDES has a decision feedback equalizer (DFE). In one embodiment, the circuit has a data processing path and an operational feedback loop coupled to said data processing path and containing an equalizer, perhaps a DFE. In that embodiment, the circuit includes an eye scanning circuit coupled to said data processing path but separate from said equalizer and configured to measure at least one dimension of an eye relative to which said equalizer is configured for operation without substantially affecting said operation.
摘要翻译：用于评估串行器解串器（SERDES）性能的电路和方法，当SERDES具有判决反馈均衡器（DFE）时特别有利。在一个实施例中，电路具有耦合到所述数据处理路径并且包含均衡器（可能是DFE）的数据处理路径和操作反馈回路。在该实施例中，电路包括耦合到所述数据处理路径但与所述均衡器分离的眼睛扫描电路，并配置成测量眼睛的至少一个尺寸，相对于该尺寸，所述均衡器构造成用于操作而基本上不影响所述操作。

30. 发明授权

US07605737B2 Data encoding in a clocked data interface 有权
标题翻译：时钟数据接口中的数据编码
公开(公告)号：US07605737B2
公开(公告)日：2009-10-20
申请号：US11696486
申请日：2007-04-04
申请人： Robert F. Payne , Richard M. Prentice
发明人： Robert F. Payne , Richard M. Prentice
IPC分类号： H03M1/12
CPC分类号： H04L7/0008 , H04L7/04
摘要： One embodiment of the present invention includes a data transmission system. The system comprises a data transmitter that provides a plurality of data bits over at least one data line. The data transmitter comprises a clock that provides a clock signal associated with timing for latching the plurality of data bits and a data encoder configured to encode error data associated with the data transmission system in the clock signal.
摘要翻译：本发明的一个实施例包括数据传输系统。该系统包括在至少一条数据线上提供多个数据位的数据发送器。数据发射机包括提供与用于锁存多个数据位的定时相关联的时钟信号的时钟和被配置为在时钟信号中对与数据传输系统相关联的错误数据进行编码的数据编码器。

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