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    • 27. 发明授权
    • Log-structured temporal shadow store
    • 日志结构的时间影子存储
    • US07257690B1
    • 2007-08-14
    • US10966968
    • 2004-10-15
    • Robert Baird
    • Robert Baird
    • G06F12/16
    • G06F11/1471G06F11/2056Y10S707/99953Y10S707/99955
    • A log-structured temporal shadow store may comprise a logical storage aggregation including a plurality of blocks, a log-structured storage device, and shadow management software. The log-structured storage device may include a plurality of log entries, where each log entry includes one or more modified blocks of the logical storage aggregation and an index to the modified blocks. In response to a new batch of changes to the logical storage aggregation, the shadow management software may be configured to append a new log entry to the log-structured storage device, including newly modified blocks and an index to the newly modified blocks. The index may be organized as a modified B+ tree, and the log-structured storage device may be a logical volume, such as a mirrored logical volume.
    • 日志结构化时间影子存储可以包括包括多个块的逻辑存储聚合,日志结构化存储设备和影子管理软件。 日志结构存储设备可以包括多个日志条目,其中每个日志条目包括逻辑存储聚合的一个或多个修改的块以及修改的块的索引。 为了响应对逻辑存储聚合的新的一批更改,可以将影子管理软件配置为将新的日志条目附加到日志结构化存储设备,包括新修改的块和对新修改的块的索引。 索引可以被组织为修改的B +树,并且日志结构存储设备可以是逻辑卷,诸如镜像逻辑卷。
    • 28. 发明申请
    • Superjunction power MOSFET
    • 超结功率MOSFET
    • US20070132020A1
    • 2007-06-14
    • US11304196
    • 2005-12-14
    • Edouard de FresartRobert BairdGanming Qin
    • Edouard de FresartRobert BairdGanming Qin
    • H01L29/76
    • H01L29/7802H01L29/0634H01L29/0873H01L29/0878H01L29/1095H01L29/456H01L29/4933H01L29/66719H01L29/7809H01L29/7811
    • Methods and apparatus are provided for TMOS devices, comprising multiple N-type source regions, electrically in parallel, located in multiple P-body regions separated by N-type JFET regions at a first surface. The gate overlies the body channel regions and the JFET region lying between the body regions. The JFET region communicates with an underlying drain region via an N-epi region. Ion implantation and heat treatment are used to tailor the net active doping concentration Nd in the JFET region of length Lacc and net active doping concentration Na in the P-body regions of length Lbody so that a charge balance relationship (Lbody*Na)=k1*(Lacc*Nd) between P-body and JFET regions is satisfied, where k1 is about 0.6≦k1≦1.4. The entire device can be fabricated using planar technology and the charge balanced regions need not extend through the underlying N-epi region to the drain.
    • 提供了用于TMOS器件的方法和装置,其包括并联的多个N型源极区域,位于在第一表面处由N型JFET区域分离的多个P体区域中。 栅极覆盖身体通道区域和位于身体区域之间的JFET区域。 JFET区域经由N-epi区域与下面的漏极区域连通。 离子注入和热处理用于定制长度为L的JFET区域中的净有源掺杂浓度N sub和净活性掺杂浓度N a, 在长度为L <! - SIPO - >本体的P体区域中,电荷平衡关系(L <! - SIPO - >) 满足P体和JFET区之间的> 1 *(L N N D D),其中k 1是约 0.6 <= K 1 <= 1.4。 整个器件可以使用平面技术制造,并且电荷平衡区域不需要延伸通过下面的N-epi区域到漏极。