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21. 发明授权

US07103489B2 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
公开(公告)号：US07103489B2
公开(公告)日：2006-09-05
申请号：US10924303
申请日：2004-08-23
申请人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
IPC分类号： G06F19/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.

22. 发明授权

US06856925B2 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
公开(公告)号：US06856925B2
公开(公告)日：2005-02-15
申请号：US10269349
申请日：2002-10-11
申请人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
IPC分类号： H03D7/12 , H04B1/10 , G06F19/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.

23. 发明授权

US07692504B2 Oscillator system, method of providing a resonating signal and a communications system employing the same 有权
标题翻译：振荡器系统，提供谐振信号的方法和采用该谐振信号的通信系统
公开(公告)号：US07692504B2
公开(公告)日：2010-04-06
申请号：US12030123
申请日：2008-02-12
申请人： Chih-Ming Hung , Robert B. Staszewski , Dirk Leipol
发明人： Chih-Ming Hung , Robert B. Staszewski , Dirk Leipol
IPC分类号： H03B5/18
CPC分类号： H03B5/08
摘要： An nth-order oscillator system for providing a resonating signal, a method of generating a resonating signal and a communications system. In one embodiment, the nth-order oscillator system, n being greater than two, includes (1) an amplifier configured to provide an intermediate signal and (2) a feedback loop including an nth-order complex LC tank and configured to generate the resonating signal by feeding back a complex-filtered form of the intermediate signal to the amplifier.
摘要翻译：用于提供谐振信号的n阶振荡器系统，产生谐振信号的方法和通信系统。在一个实施例中，n大于2的n阶振荡器系统包括（1）被配置为提供中间信号的放大器和（2）包括第n级复数LC容器的反馈回路，并被配置为产生谐振信号通过将中间信号的复数滤波形式反馈到放大器。

24. 发明申请

US20110261871A1 ALL-DIGITAL FREQUENCY SYNTHESIS WITH DCO GAIN CALCULATION 有权
标题翻译：全数字频率合成与DCO增益计算
公开(公告)号：US20110261871A1
公开(公告)日：2011-10-27
申请号：US13175594
申请日：2011-07-01
申请人： Robert B. Staszewski , Dirk Leipold , John Wallberg
发明人： Robert B. Staszewski , Dirk Leipold , John Wallberg
IPC分类号： H04B17/00
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (Δfmax) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator.
摘要翻译：全数字频率合成器架构围绕数字控制振荡器（DCO）构建，该振荡器响应于数字调谐字（OTW）进行调谐。在示例性实施例中：（1）数字控制振荡器的增益特性（KDCO）可以通过在振荡频率中的已知变化（＆Dgr; fmax）之前和之后观察数字控制字来确定; 和（2）调谐字的一部分（TUNE_TF）可以被抖动（1202），并且所得到的抖动部分（dkTF）然后可以被施加到数字控制振荡器内的可切换装置的控制输入。

25. 发明授权

US08000428B2 All-digital frequency synthesis with DCO gain calculation 有权
标题翻译：全数字频率合成采用DCO增益计算
公开(公告)号：US08000428B2
公开(公告)日：2011-08-16
申请号：US10302029
申请日：2002-11-22
申请人： Robert B. Staszewski , Dirk Leipold , John Wallberg
发明人： Robert B. Staszewski , Dirk Leipold , John Wallberg
IPC分类号： H04L7/00
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (Δfmax) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator.
摘要翻译：全数字频率合成器架构围绕数字控制振荡器（DCO）构建，该振荡器响应于数字调谐字（OTW）进行调谐。在示例性实施例中：（1）数字控制振荡器的增益特性（KDCO）可以通过在振荡频率中的已知变化（＆Dgr; fmax）之前和之后观察数字控制字来确定; 和（2）调谐字的一部分（TUNE_TF）可以被抖动（1202），并且所得到的抖动部分（dkTF）然后可以被施加到数字控制振荡器内的可切换装置的控制输入。

26. 发明授权

US07813462B2 Method of defining semiconductor fabrication process utilizing transistor inverter delay period 有权
标题翻译：利用晶体管反相器延迟周期定义半导体制造工艺的方法
公开(公告)号：US07813462B2
公开(公告)日：2010-10-12
申请号：US11550878
申请日：2006-10-19
申请人： Elida Isabel de Obaldia , Robert B. Staszewski , Dirk Leipold
发明人： Elida Isabel de Obaldia , Robert B. Staszewski , Dirk Leipold
IPC分类号： H03D3/24
CPC分类号： H04L27/361 , H03L7/091 , H03L7/0991 , H03L7/1806
摘要： A novel method and apparatus for defining process variation in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The method and apparatus provide direct measurement of fabrication process variation in circuits without requiring any additional test equipment by utilizing a time to digital converter (TDC) circuit already present in the chip. The TDC circuit relies on the time delay in an inverter chain to sample a high speed CKV clock using a slow FREF clock. Calculation of inverse time provides a direct correlation for fabrication process variation in each die.
摘要翻译：一种用于定义数字RF处理器（DRP）中的处理变化的新颖方法和装置。本发明非常适用于结合了大量数字逻辑电路的高度集成的片上系统（SoC）无线电解决方案。该方法和装置提供对电路中制造工艺变化的直接测量，而不需要使用已经存在于芯片中的时间 - 数字转换器（TDC）电路的任何额外的测试设备。 TDC电路依赖于逆变器链中的时间延迟，使用缓慢的FREF时钟采样高速CKV时钟。逆时间的计算提供了每个模具中制造工艺变化的直接相关性。

27. 发明授权

US07667511B2 Efficient pulse amplitude modulation transmit modulation 有权
标题翻译：有效的脉冲幅度调制发射调制
公开(公告)号：US07667511B2
公开(公告)日：2010-02-23
申请号：US11195060
申请日：2005-08-02
申请人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
发明人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
IPC分类号： H03K3/017
CPC分类号： H03F1/02 , H03F1/0205 , H03F3/217 , H03F3/2171 , H03F3/2176 , H03F2200/331 , H03K5/06 , H03K7/02 , H04B1/0483 , H04B2001/0491
摘要： Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.
摘要翻译：由PAM调制器提供有效的PAM发射调制，PAM调制器包括提供时钟信号CKV（408）的振荡器（404）。时钟信号408和时钟信号的延迟版本（CKV_DLY）420被提供给逻辑门（414）。逻辑门（414）的输出用作射频功率放大器（416）的功率放大器输入信号（PA_IN）。根据CKV时钟信号（408）和CKV_DLY延迟时钟信号（420）的相对时间延迟，可以控制逻辑门（414）占空比的定时和占空比。占空比或脉冲宽度变化影响功率放大器的导通时间（416）; 从而建立RF输出振幅。

28. 发明授权

US06959049B2 Multi-tap, digital-pulse-driven mixer 有权
标题翻译：多抽头，数字脉冲驱动搅拌机
公开(公告)号：US06959049B2
公开(公告)日：2005-10-25
申请号：US09828338
申请日：2001-04-06
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H03D7/00 , H03D7/12 , H03D7/14 , H04B1/26 , H04B1/28 , H03K9/00 , H04B1/16 , H04L27/08
CPC分类号： H03D7/1441 , H03D7/125 , H03D7/1466 , H03D7/1475 , H04B1/28
摘要： A multi-tap, digital-pulse-driven mixer advantageously avoids local oscillator (11) leakage by shifting the local oscillator frequency (FLO) out of the received frequency band. Low noise figures are advantageously realized by the use of digital pulses (51, 52) as mixer drive signals (16).
摘要翻译：多抽头数字脉冲驱动混频器有利地通过将本地振荡器频率（F LO LO）从接收频带中移位来避免本地振荡器（11）的泄漏。通过使用数字脉冲（51,52）作为混频器驱动信号（16），有利地实现了低噪声系数。

29. 发明授权

US06429693B1 Digital fractional phase detector 有权
$Digital fractional phase detector$
标题翻译：数字分数相位检测器
公开(公告)号：US06429693B1
公开(公告)日：2002-08-06
申请号：US09608317
申请日：2000-06-30
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H03D324
CPC分类号： H03L7/085 , H03L7/087 , H03L7/091 , H03L2207/50
摘要： A digital fractional phase detector is provided to realize a frequency synthesizer architecture that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information. The digital fractional phase detector is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the VCO output clock and a reference clock by using a time-to-digital converter to express the time difference as a digital word for use by the frequency synthesizer.
摘要翻译：提供数字分数相位检测器以实现频率合成器架构，其自然地将发射机调制能力与宽带全数字PLL调制方案相结合，以通过在同步相域中操作来最大化数字密集型实现。通过实施与参考计算相关联的定时调整，跨数字控制VCO提供同步逻辑，并且与VCO输出时钟同步，以允许频率控制字包含信道信息和发送调制信息。数字分数相位检测器能够容纳量化方案，以通过使用时间 - 数字转换器来测量VCO输出时钟的显着边缘与参考时钟之间的分数延迟差，以将时差表示为要使用的数字字由频率合成器。

30. 发明授权

US07330082B2 Oscillator system, method of providing a resonating signal and a communications system employing the same 有权
标题翻译：振荡器系统，提供谐振信号的方法和采用该谐振信号的通信系统
公开(公告)号：US07330082B2
公开(公告)日：2008-02-12
申请号：US10924220
申请日：2004-08-23
申请人： Chih-Ming Hung , Robert B. Staszewski , Dirk Leipol
发明人： Chih-Ming Hung , Robert B. Staszewski , Dirk Leipol
IPC分类号： H03B5/18
CPC分类号： H03B5/08
摘要： An nth-order oscillator system for providing a resonating signal, a method of generating a resonating signal and a communications system. In one embodiment, the nth-order oscillator system, n being greater than two, includes (1) an amplifier configured to provide an intermediate signal and (2) a feedback loop including an nth-order complex LC tank and configured to generate the resonating signal by feeding back a complex-filtered form of the intermediate signal to the amplifier.
摘要翻译：一种用于提供谐振信号的第n / O级振荡器系统，产生谐振信号的方法和通信系统。在一个实施例中，n大于2的n阶振荡器系统包括（1）被配置为提供中间信号的放大器和（2）包括n + 并且被配置为通过将中间信号的复数滤波形式反馈到放大器来产生谐振信号。

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