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1. 发明授权

US07667511B2 Efficient pulse amplitude modulation transmit modulation 有权
标题翻译：有效的脉冲幅度调制发射调制
公开(公告)号：US07667511B2
公开(公告)日：2010-02-23
申请号：US11195060
申请日：2005-08-02
申请人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
发明人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
IPC分类号： H03K3/017
CPC分类号： H03F1/02 , H03F1/0205 , H03F3/217 , H03F3/2171 , H03F3/2176 , H03F2200/331 , H03K5/06 , H03K7/02 , H04B1/0483 , H04B2001/0491
摘要： Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.
摘要翻译：由PAM调制器提供有效的PAM发射调制，PAM调制器包括提供时钟信号CKV（408）的振荡器（404）。时钟信号408和时钟信号的延迟版本（CKV_DLY）420被提供给逻辑门（414）。逻辑门（414）的输出用作射频功率放大器（416）的功率放大器输入信号（PA_IN）。根据CKV时钟信号（408）和CKV_DLY延迟时钟信号（420）的相对时间延迟，可以控制逻辑门（414）占空比的定时和占空比。占空比或脉冲宽度变化影响功率放大器的导通时间（416）; 从而建立RF输出振幅。

2. 发明授权

US06924681B2 Efficient pulse amplitude modulation transmit modulation 有权
标题翻译：有效的脉冲幅度调制发射调制
公开(公告)号：US06924681B2
公开(公告)日：2005-08-02
申请号：US10154093
申请日：2002-05-22
申请人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
发明人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
IPC分类号： H03F1/02 , H03F1/06 , H03F3/217 , H03K3/00 , H03K3/017 , H03K5/06 , H03K7/02 , H04B1/04
CPC分类号： H03F1/02 , H03F1/0205 , H03F3/217 , H03F3/2171 , H03F3/2176 , H03F2200/331 , H03K5/06 , H03K7/02 , H04B1/0483 , H04B2001/0491
摘要： Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.
摘要翻译：由PAM调制器提供有效的PAM发射调制，PAM调制器包括提供时钟信号CKV（408）的振荡器（404）。时钟信号408和时钟信号的延迟版本（CKV_DLY）420被提供给逻辑门（414）。逻辑门（414）的输出用作射频功率放大器（416）的功率放大器输入信号（PA_IN）。根据CKV时钟信号（408）和CKV_DLY延迟时钟信号（420）的相对时间延迟，可以控制逻辑门（414）占空比的定时和占空比。占空比或脉冲宽度变化影响功率放大器的导通时间（416）; 从而建立RF输出振幅。

3. 发明申请

US20090196384A1 Direct Radio Frequency (RF) Sampling With Recursive Filtering Method 审中-公开
标题翻译：直接射频（RF）采样递归滤波方法
公开(公告)号：US20090196384A1
公开(公告)日：2009-08-06
申请号：US12334268
申请日：2008-12-12
申请人： Robert B. Staszewski , Khurram Muhammad , Kenneth J. Maggio , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Kenneth J. Maggio , Dirk Leipold
IPC分类号： H03D1/04
CPC分类号： H03D7/125 , H04B1/1036
摘要： A radio receiver 2000 with a sampling mixer 1100 for creating a discrete-time sample stream by directly sampling an RF current with history and rotating capacitors 1111 and 1112, wherein the accumulated charge on the rotating capacitors is read-out to produce a sample. The mixer provides immunity to noise glitches by predicting the occurrence of the glitch (or detecting a significant difference between observed and predicted samples) and creating corrected samples for the corrupted samples. These corrected samples can be created with special circuitry 1933 (digital) or in the mixer 1100 (analog).
摘要翻译：具有采样混合器1100的无线电接收机2000，用于通过用历史和旋转电容器1111和1112直接采样RF电流来产生离散时间采样流，其中读出旋转电容器上的累积电荷以产生样本。混合器通过预测毛刺的发生（或检测观察到的和预测的样品之间的显着差异）并为损坏的样品产生校正的样品来提供对噪声毛刺的免疫。这些校正样本可以用专用电路1933（数字）或混合器1100（模拟）来创建。

4. 发明授权

US07519135B2 Direct radio frequency (RF) sampling with recursive filtering method 有权
标题翻译：直接射频（RF）采样采用递归滤波法
公开(公告)号：US07519135B2
公开(公告)日：2009-04-14
申请号：US10190867
申请日：2002-07-08
申请人： Robert B. Staszewski , Khurram Muhammad , Kenneth J. Maggio , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Kenneth J. Maggio , Dirk Leipold
IPC分类号： H03K5/01
CPC分类号： H03D7/125 , H04B1/1036
摘要： A radio receiver 2000 with a sampling mixer 1100 for creating a discrete-time sample stream by directly sampling an RF current with history and rotating capacitors 1111 and 1112, wherein the accumulated charge on the rotating capacitors is read-out to produce a sample. The mixer provides immunity to noise glitches by predicting the occurrence of the glitch (or detecting a significant difference between observed and predicted samples) and creating corrected samples for the corrupted samples. These corrected samples can be created with special circuitry 1933 (digital) or in the mixer 1100 (analog).
摘要翻译：具有采样混合器1100的无线电接收机2000，用于通过用历史和旋转电容器1111和1112直接采样RF电流来产生离散时间采样流，其中读出旋转电容器上的累积电荷以产生样本。混合器通过预测毛刺的发生（或检测观察到的和预测的样品之间的显着差异）并为损坏的样品产生校正的样品来提供对噪声毛刺的免疫。这些校正样本可以用专用电路1933（数字）或混合器1100（模拟）来创建。

5. 发明授权

US08155256B2 Method and apparatus for asynchronous clock retiming 有权
标题翻译：用于异步时钟重新定时的方法和装置
公开(公告)号：US08155256B2
公开(公告)日：2012-04-10
申请号：US09969307
申请日：2001-10-02
申请人： Robert B. Staszewski , Kenneth J. Maggio , Dirk D. Leipold
发明人： Robert B. Staszewski , Kenneth J. Maggio , Dirk D. Leipold
IPC分类号： H04L7/00
CPC分类号： H03L7/18 , H03L7/085 , H03L7/091 , H03L2207/50
摘要： A time to digital converter is used to determine which edge of the higher frequency clock (oversampling clock) is farther away from the edge of the lower frequency timing signal. At the same time, the oversampling clock performs sampling of the timing signal by two registers: one on the rising edge and the other on the falling edge. Then, the register of “better quality” retiming, as determined by the fractional phase detector decision, is selected to provide the retimed output.
摘要翻译：使用时间到数字转换器来确定较高频率时钟（过采样时钟）的哪个边缘比较低频率定时信号的边缘更远。同时，过采样时钟通过两个寄存器执行定时信号的采样：一个在上升沿，另一个在下降沿。然后，选择由分数阶段检测器决定确定的“更好质量”重新定时的寄存器，以提供重定时输出。

6. 发明授权

US06851493B2 Digital PLL with gear shift 有权
标题翻译：数字PLL与换档
公开(公告)号：US06851493B2
公开(公告)日：2005-02-08
申请号：US09728180
申请日：2000-12-01
申请人： Robert B. Staszewski , Kenneth J. Maggio
发明人： Robert B. Staszewski , Kenneth J. Maggio
IPC分类号： H03L7/093 , H03L7/06 , H03L7/099 , H03L7/107 , H03L7/18 , H03D3/24
CPC分类号： H03L7/107 , H03L7/0991 , H03L7/1806
摘要： A PLL synthesizer (100) includes a gear-shifting scheme of the PLL loop gain constant, α. During frequency/phase acquisition, a larger loop gain constant, α1 is used such that the resulting phase error is within limits. After the frequency/phase gets acquired, the developed phase error, which is a rough indication of the frequency offset is in a steady-state condition. While transitioning into the tracking mode, the DC offset is added to the DCO tuning signal preferably the DC offset is added to the phase error signal and the loop constant is reduced from α1 to α2. This scheme provides for hitless operation, while requiring a low dynamic range of the phase detector (101).
摘要翻译： PLL合成器（100）包括PLL环路增益常数α的换档方案。在频率/相位采集期间，使用较大的环路增益常数α1，使得所得到的相位误差在限度内。在获取频率/相位之后，发展的相位误差是频率偏移的粗略指示处于稳态条件。当转换到跟踪模式时，DC偏移被添加到DCO调谐信号中，优选地，DC偏移被加到相位误差信号上，并且环路常数从α1减小到α2。该方案提供了无脉冲操作，同时需要相位检测器（101）的低动态范围。

7. 发明授权

US07003276B2 Subsampling communication receiver architecture with gain control and RSSI generation 有权
标题翻译：采样增益控制和RSSI生成的通信接收机架构
公开(公告)号：US07003276B2
公开(公告)日：2006-02-21
申请号：US10132025
申请日：2002-04-25
申请人： Khurram Muhammad , Dirk Leipold , Kenneth J. Maggio
发明人： Khurram Muhammad , Dirk Leipold , Kenneth J. Maggio
IPC分类号： H04B1/26
CPC分类号： H04B1/0025 , H03H15/00 , H03H19/004 , H04B1/0003 , H04B1/28 , H04L27/24
摘要： A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional-cycles of the first voltage waveform are obtained. The samples are combined to produce the second voltage waveform. The samples can be manipulated to provide gain adjustment to the second voltage waveform. The samples are obtained by charging a sampling capacitance in response to a current waveform that corresponds to the first voltage waveform. The use of different sampling capacitances during respective predetermined time intervals permits the signal strength of the first waveform to be determined from observation of the second waveform.
摘要翻译：第一周期性电压波形（20）被下变频成第二周期性电压波形（35,36）。获得分别表示第一电压波形的相应分数周期下的面积的多个时间上不同的样本（SA 1，SA 2 ...）。将样品组合以产生第二电压波形。可以操作样品以对第二电压波形提供增益调整。通过响应于对应于第一电压波形的电流波形对采样电容进行充电来获得样本。在各个预定时间间隔期间使用不同的采样电容允许通过观察第二波形来确定第一波形的信号强度。

8. 发明授权

US06282044B1 8V ring clamp circuit 有权
标题翻译： 8V环形钳位电路
公开(公告)号：US06282044B1
公开(公告)日：2001-08-28
申请号：US09286187
申请日：1999-04-05
申请人： Patrick M. Teterud , Kenneth J. Maggio
发明人： Patrick M. Teterud , Kenneth J. Maggio
IPC分类号： G11B502
CPC分类号： G11B5/022 , G11B5/012 , G11B5/02 , G11B2005/0013
摘要： A clamp circuit for clamping a terminal of an H-bridge circuit. The clamp circuit is capable of being applied to a voltage in excess of 5V including 8 volts.
摘要翻译：用于钳位H桥电路端子的钳位电路。钳位电路能够施加到超过5V的电压，包括8伏特。

9. 发明授权

US6020699A Circuitry and method for controllable slew rate 失效
标题翻译：可控转换速率的电路和方法
公开(公告)号：US6020699A
公开(公告)日：2000-02-01
申请号：US926735
申请日：1997-09-10
申请人： Kenneth J. Maggio , Rolf Lagerquist
发明人： Kenneth J. Maggio , Rolf Lagerquist
IPC分类号： G11B19/20 , H02P6/10 , H02P6/14 , H02K23/00
CPC分类号： G11B19/2009 , H02P6/10 , H02P6/14
摘要： A circuit for controlling the slew rate in the stator coils of a polyphase, dc motor is provided. The circuit includes a first steady state control circuitry (12), a low side commutation circuitry (60), a second steady state control circuitry (62), and a high side commutation circuitry (64). The first steady state control circuitry (12) regulates the current through an A-coil (14) and a C-coil (18) after a high side commutation. The A-coil (14) couples to a voltage source through an HSDA (22) at one end and couples to the C-coil (18) through a center tap at the other end. The C-coil (18) couples to an LSDC (24) at its other end during this state. The low side commutation circuitry (60) performs a low side commutation by controlling the current slew rate of the C-coil (18) and a B-coil (16) as the current in the C-coil (18) is reduced to zero and the current in the B-coil (16) is increased from zero to a steady state level. The B-coil (16) couples to the center tap on one end and to an LSDB (52) at its other end. The second steady state control circuitry (62) regulates the current through the A-coil (14) and a B-coil (16) after a low side commutation. The high side commutation circuitry (64) performs a high side commutation by controlling the current slew rate of the C-coil (18) and the A-coil (14) as the current in the A-coil (14) is reduced to zero and the current in the C-coil (18) is increased from zero to a steady state level. The C-coil (18) couples between an HSDC (66) and the center tap during this state.
摘要翻译：提供用于控制多相直流电动机的定子线圈中的转换速率的电路。该电路包括第一稳态控制电路（12），低侧换向电路（60），第二稳态控制电路（62）和高侧换向电路（64）。第一稳态控制电路（12）在高侧换向之后调节通过A线圈（14）和C线圈（18）的电流。 A线圈（14）在一端通过HSDA（22）耦合到电压源，并通过另一端的中心抽头耦合到C线圈（18）。在此状态下，C线圈（18）在另一端耦合到LSDC（24）。低侧换向电路（60）通过控制C线圈（18）和B线圈（16）的电流转换速率来执行低侧换向，因为C线圈（18）中的电流减小到零并且B线圈（16）中的电流从零增加到稳态电平。 B线圈（16）在一端耦合到中心抽头，并在另一端连接到LSDB（52）。第二稳态控制电路（62）在低侧换向之后调节通过A线圈（14）的电流和B线圈（16）。当A线圈（14）中的电流减小到零时，通过控制C线圈（18）和A线圈（14）的电流转换速率，高侧换向电路（64）执行高侧换向并且C线圈（18）中的电流从零增加到稳态水平。在这种状态下，C线圈（18）在HSDC（66）和中心抽头之间耦合。

10. 发明授权

US5867001A Trim circuitry and method for accuracy in current sensing 失效
标题翻译：修剪电路和电流检测精度的方法
公开(公告)号：US5867001A
公开(公告)日：1999-02-02
申请号：US925242
申请日：1997-09-08
申请人： Rolf Lagerquist , William R. Krenik , Kenneth J. Maggio , Patrick G. O'Farrell
发明人： Rolf Lagerquist , William R. Krenik , Kenneth J. Maggio , Patrick G. O'Farrell
IPC分类号： G01R19/00 , H02P6/00 , H02P6/10 , H02P7/00
CPC分类号： H02P6/10 , H02P6/28
摘要： A motor driver circuit (12) for providing drive signals to stator coils of a polyphase dc motor (10) includes a plurality of current paths, each connected between a supply voltage and a reference potential. Each current path includes two driver transistors (14,20, 16,22, 18,24), a node (A, B, C) of each of the stator coils being connectable between the driver transistors in respective current flow paths. A commutator (26) is connected to operate the driver transistors in a sequence in which drive currents are delivered for application in a predetermined sequence to the stator coils. A plurality of sensing transistors (32) are connected to produce a mirror current which mirrors a mirrored current in an associated driver transistor (20) in a respective current flow path. Circuitry (26) is provided which is responsive to the mirror currents of the sensing transistors to control the amplitudes of the currents in the associated driver transistor in a respective current flow path. At least one trim transistor (51-55) is connected in parallel with a respective one of the sensing transistors (50), and a programmable circuit (48) is connected to selectively activate the at least one trim transistor to adjust the amplitudes of the mirrored currents in the current flow path with which the sensing transistor with which the at least one trim transistor is associated.
摘要翻译：用于向多相直流电动机（10）的定子线圈提供驱动信号的电机驱动器电路（12）包括多个电流路径，每个电流路径连接在电源电压和参考电位之间。每个电流路径包括两个驱动器晶体管（14,20,16,22,18,24），每个定子线圈的节点（A，B，C）可在相应的电流流动路径中的驱动器晶体管之间连接。换向器（26）被连接以按驱动电流被输送的顺序来操作驱动器晶体管，以便以预定顺序施加到定子线圈。连接多个感测晶体管（32）以产生镜电流，其反映相应的电流流动路径中相关联的驱动晶体管（20）中的镜像电流。提供电路（26），其响应于感测晶体管的镜像电流来控制相应的电流流动路径中相关联的驱动器晶体管中的电流的幅度。至少一个微调晶体管（51-55）与感测晶体管（50）中的相应一个并联连接，并且可编程电路（48）被连接以选择性地激活所述至少一个修整晶体管以调整电流流动路径中与至少一个修整晶体管相关联的感测晶体管的镜像电流。

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