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21. 发明授权

US06467001B1 VLSI chip macro interface 失效
标题翻译： VLSI芯片宏接口
公开(公告)号：US06467001B1
公开(公告)日：2002-10-15
申请号：US09374222
申请日：1999-08-13
申请人： Mandy Alexander Gray , Michael J. Palmer , Ian David Judd
发明人： Mandy Alexander Gray , Michael J. Palmer , Ian David Judd
IPC分类号： G06F1336
CPC分类号： H04L49/101
摘要： The present invention provides a method and a system for connecting together, in a VLSI chip, a plurality of macros which require data flow connections between each other. A simple standard interface is realised between all macros. Any number of macros can be connected together, also allowing concurrent transactions between 4 or more macros using a cross-bar switch. Each macro may be a master (capable of requesting connections), a slave (capable of receiving connections from a master) or both. The centralised inter-connect logic includes three major components: the cross-bar switch, which makes the connections between the macros, the address decoder, which determines which slave each master wishes to connect to and an arbiter, which arbitrates between the macros when two or more masters request a connection simultaneously.
摘要翻译：本发明提供了一种用于在VLSI芯片中将需要相互数据流连接的多个宏连接在一起的方法和系统。所有宏之间实现简单的标准接口。任何数量的宏都可以连接在一起，也允许使用交叉开关的4个或更多宏之间的并发事务。每个宏可以是主（能够请求连接），从机（能够从主机接收连接）或两者。集中式互连逻辑包括三个主要部分：交叉开关，它们使得宏之间的连接，地址解码器确定每个主机希望连接的从属和仲裁器，它们在宏之间进行仲裁或更多的主人同时请求连接。

22. 发明授权

US5893138A System and method for improving channel hardware performance for an array controller 失效
标题翻译：用于提高阵列控制器通道硬件性能的系统和方法
公开(公告)号：US5893138A
公开(公告)日：1999-04-06
申请号：US537649
申请日：1995-10-02
申请人： Ian David Judd , Stephen G. Luning
发明人： Ian David Judd , Stephen G. Luning
IPC分类号： G06F3/06 , G11B17/22 , G06F13/12
CPC分类号： G06F3/0601 , G06F2003/0692
摘要： Disclosed is an array controller for controlling the transfer of data from a host system to an array of data storage devices, comprising a processor connected via a local bus to a data buffer in which data is staged during said transfer. The array controller is provided with a buffer controller for controlling the operation of the buffer and is further provided with channel hardware for manifesting a plurality of data channels, selectable by the local bus address, over which data is transferred in and out of the data buffer.
摘要翻译：公开了一种用于控制从主机系统到数据存储设备阵列的数据传输的阵列控制器，包括经由本地总线连接到数据缓冲器的处理器，在数据缓冲器中数据在所述传送期间进行。阵列控制器设置有用于控制缓冲器的操作的缓冲器控制器，还提供有用于显示多个数据通道的通道硬件，可由本地总线地址选择，通过该数据通道将数据传入和传出数据缓冲器。

23. 发明授权

US08326897B2 Apparatus and method for managing data storage 失效
标题翻译：用于管理数据存储的装置和方法
公开(公告)号：US08326897B2
公开(公告)日：2012-12-04
申请号：US12338931
申请日：2008-12-18
申请人： Henry Esmond Butterworth , Ian David Judd
发明人： Henry Esmond Butterworth , Ian David Judd
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F11/1435 , G06F11/1453 , G06F12/0808 , G06F17/30218 , G06F2201/84 , G06F2212/62
摘要： An apparatus for controlling a log-structured data storage system, operable with a first log-structured data storage area for storing data, comprises a metadata storage component for controlling the first log-structured data storage area and comprising a second log-structured data storage area for storing metadata; and means for nesting the second log-structured data storage area for storing metadata within the first log-structured data storage area. The apparatus may further comprise at least a third log-structured data storage area for storing further metadata, and means for nesting the at least a third log-structured data storage area within the second log-structured data storage area.
摘要翻译：一种用于控制用于存储数据的第一对数结构化数据存储区域可操作的日志结构数据存储系统的装置，包括用于控制第一对数结构化数据存储区域的元数据存储组件，并且包括第二对数结构化数据存储用于存储元数据的区域以及用于嵌套用于在第一对数结构化数据存储区域内存储元数据的第二对数结构化数据存储区域的装置。所述设备还可以包括用于存储更多元数据的至少第三对数结构化数据存储区域，以及用于将所述至少第三日志结构化数据存储区域嵌套在所述第二对数结构化数据存储区域内的装置。

24. 发明授权

US07759820B2 Connection error avoidance for apparatus connected to a power supply 有权
标题翻译：连接到电源的设备的连接错误避免
公开(公告)号：US07759820B2
公开(公告)日：2010-07-20
申请号：US11836065
申请日：2007-08-08
申请人： Steven John Hyatt , Ian David Judd , Robert Bruce Nicholson , Paul Jonathan Ouelch , Stephen Arthur Randle , William James Scales
发明人： Steven John Hyatt , Ian David Judd , Robert Bruce Nicholson , Paul Jonathan Ouelch , Stephen Arthur Randle , William James Scales
IPC分类号： H02J9/00
CPC分类号： G06F11/2289 , Y10T307/615
摘要： According to a first general aspect of the present invention, there is provided a logic arrangement for reducing incidence of errors in connections between a power consumer apparatus and a power supply apparatus, the logic arrangement comprising: a pattern-generating component for generating an identifiable pattern in a load to be drawn from a power supply connection to a power supply apparatus; and a testing component for monitoring across a signal connection to the power supply apparatus, the testing component monitoring for a change in the load corresponding to the pattern. A positive result of the testing by the testing component indicates a correct configuration. Additional embodiments are also presented.
摘要翻译：根据本发明的第一个总体方面，提供了一种用于减少电力消耗装置和电源装置之间的连接中的错误的发生率的逻辑装置，所述逻辑装置包括：用于产生可识别图案的模式产生部件在从电源连接到电源装置的负载中; 以及用于在与电源装置的信号连接之间进行监视的测试部件，所述测试部件监视对应于所述模式的负载变化。测试组件测试的积极结果表示正确的配置。还提供了另外的实施例。

25. 发明申请

US20080256318A1 Copy Engine and a Method for Data Movement 失效
标题翻译：复制引擎和数据移动方法
公开(公告)号：US20080256318A1
公开(公告)日：2008-10-16
申请号：US12141441
申请日：2008-06-18
申请人： Carlos Francisco Fuente , Ian David Judd , Robert Bruce Nicholson , Mandy A. Stevens
发明人： Carlos Francisco Fuente , Ian David Judd , Robert Bruce Nicholson , Mandy A. Stevens
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F13/28
摘要： A copy engine (104) is provided as an interface between firmware (108) and memory space (106) for carrying out copy operations. The copy engine has a first register (202, 203) to point to a first address and a second register (204, 205) to point to a second address. One of the first and second addresses is a source address and one is a destination address for data to be copied. The copy engine (104) also has a control register (201). The control register (201) includes a count of the amount of memory space required by a copy operation, an indication of the direction of the copy operation from the first address to the second address or from the second address to the first address, and an indication of whether the first memory address is incremented or decremented. The copy engine (104) includes a locking mechanism for locking the copy engine (104) during a copy operation. The copy engine (104) also includes a serialization mechanism in which a write is made to control register (201) of zero count. If the copy engine (104) is locked, the write of zero count is retried until the existing copy operation has completed and then it will complete with no effect.
摘要翻译：提供复制引擎（104）作为固件（108）和存储器空间（106）之间的接口，用于执行复制操作。复制引擎具有指向第一地址的第一寄存器（202,203）和指向第二地址的第二寄存器（204,205）。第一和第二地址之一是源地址，一个是要复制的数据的目的地址。复制引擎（104）还具有控制寄存器（201）。控制寄存器（201）包括由复制操作所需的存储空间量的计数，从第一地址到第二地址或从第二地址到第一地址的复制操作的方向的指示，以及指示第一个存储器地址是递增还是递减。复印机（104）包括用于在复印操作期间锁定复印机（104）的锁定机构。复制引擎（104）还包括一个序列化机制，其中写入零计数的控制寄存器（201）。如果复制引擎（104）被锁定，则重试零计数，直到现有的复制操作完成，然后它将不起作用。

26. 发明申请

US20080040402A1 STORAGE MANAGEMENT SYSTEM WITH INTEGRATED CONTINUOUS DATA PROTECTION AND REMOTE COPY 失效
标题翻译：具有集成连续数据保护和远程复制的存储管理系统
公开(公告)号：US20080040402A1
公开(公告)日：2008-02-14
申请号：US11836068
申请日：2007-08-08
申请人： Ian David Judd
发明人： Ian David Judd
IPC分类号： G06F17/30
CPC分类号： G06F11/2066 , G06F11/2071 , G06F2201/855
摘要： A storage control system is adapted to operate as a primary of a remote copy pair by communicating with a secondary of the remote copy pair, and comprises: an I/O receiving component for receiving read and write commands; a continuous data protection component operatively coupled to the I/O receiving component for maintaining a continuous data protection journal; the continuous data protection journal operable to retain write I/O data items for access by subsequent read commands and to roll back the data at the primary of the remote copy pair; a remote copy controller component adapted to read the write I/O data item from the continuous data protection journal; and a remote copy transmission component operatively coupled to the remote copy controller component to transmit the write I/O data item to the secondary of the remote copy pair.
摘要翻译：存储控制系统适于通过与远程副本对的通信进行通信来操作为远程副本对的主要，并且包括：用于接收读取和写入命令的I / O接收组件; 连续数据保护组件，可操作地耦合到I / O接收组件，用于维持连续的数据保护期刊; 连续数据保护期刊可操作以保留用于由后续读取命令访问的写入I / O数据项，并且回滚远程副本对象的主要数据; 远程复制控制器组件，适于从连续数据保护期刊读取写I / O数据项; 以及可操作地耦合到所述远程复制控制器组件以将所述写I / O数据项发送到所述远程副本对的次级的远程复制传输组件。

27. 发明授权

US6128674A Method of minimizing host CPU utilization in driving an adapter by residing in system memory a command/status block a soft interrupt block and a status block queue 失效
标题翻译：通过驻留在系统存储器中来最小化驱动适配器的主机CPU利用率的方法，命令/状态块软中断块和状态块队列
公开(公告)号：US6128674A
公开(公告)日：2000-10-03
申请号：US908888
申请日：1997-08-08
申请人： Bruce Leroy Beukema , Patrick Allen Buckland , Wen-Tzer Thomas Chen , David Arlen Elko , Ian David Judd , Renato John Recio
发明人： Bruce Leroy Beukema , Patrick Allen Buckland , Wen-Tzer Thomas Chen , David Arlen Elko , Ian David Judd , Renato John Recio
IPC分类号： G06F3/00 , G06F9/06 , G06F12/08 , G06F13/28
CPC分类号： G06F12/0835
摘要： The system I/O interface and its data structure are designed to minimize the host CPU utilization in driving an adapter. The interface is also designed to reduce the system interference in processing I/O requests. To eliminate the need of using PIO instructions, the command/status blocks for exchanging messages between the system and the adapter reside in the system memory. The data structure is designed to avoid "share write" entries in order to further minimize the overhead of maintaining each coherency when updating an entry in the cache either concurrently or sequentially by both adapter and system CPU. Further, the data structure of the control and status blocks is resided in the system memory. The system CPU uses STORE instruction to prepare control blocks and LOAD instruction to read from completion status blocks; while the adapter will rely on its DMA engine to move data to/from system memory in accessing control/status blocks.
摘要翻译：系统I / O接口及其数据结构旨在最大限度地减少驱动适配器时的主机CPU利用率。该接口还旨在减少处理I / O请求时的系统干扰。为了不需要使用PIO指令，系统和适配器之间交换消息的命令/状态块驻留在系统内存中。数据结构旨在避免“共享写入”条目，以便在适配器和系统CPU同时或顺序更新缓存中的条目时进一步最小化维护每个一致性的开销。此外，控制和状态块的数据结构驻留在系统存储器中。系统CPU使用STORE指令准备控制块和LOAD指令，从完成状态块读取; 而适配器将依靠其DMA引擎在访问控制/状态块时将数据移入/移出系统内存。

28. 发明申请

US20120303902A1 APPARATUS AND METHOD FOR MANAGING DATA STORAGE 有权
标题翻译：用于管理数据存储的装置和方法
公开(公告)号：US20120303902A1
公开(公告)日：2012-11-29
申请号：US13569067
申请日：2012-08-07
申请人： Henry Esmond Butterworth , Ian David Judd
发明人： Henry Esmond Butterworth , Ian David Judd
IPC分类号： G06F12/12 , G06F12/16
CPC分类号： G06F11/1435 , G06F11/1453 , G06F12/0808 , G06F17/30218 , G06F2201/84 , G06F2212/62
摘要： An apparatus for controlling a log-structured data storage system, operable with a first log-structured data storage area for storing data, comprises a metadata storage component for controlling the first log-structured data storage area and comprising a second log-structured data storage area for storing metadata; and means for nesting the second log-structured data storage area for storing metadata within the first log-structured data storage area. The apparatus may further comprise at least a third log-structured data storage area for storing further metadata, and means for nesting the at least a third log-structured data storage area within the second log-structured data storage area.
摘要翻译：一种用于控制用于存储数据的第一对数结构化数据存储区域可操作的日志结构数据存储系统的装置，包括用于控制第一对数结构化数据存储区域的元数据存储组件，并且包括第二对数结构化数据存储用于存储元数据的区域以及用于嵌套用于在第一对数结构化数据存储区域内存储元数据的第二对数结构化数据存储区域的装置。所述设备还可以包括用于存储更多元数据的至少第三对数结构化数据存储区域，以及用于将所述至少第三日志结构化数据存储区域嵌套在所述第二对数结构化数据存储区域内的装置。

29. 发明授权

US07793062B2 Copy engine and a method for data movement 失效
标题翻译：复制引擎和数据移动方法
公开(公告)号：US07793062B2
公开(公告)日：2010-09-07
申请号：US12141441
申请日：2008-06-18
申请人： Carlos Francisco Fuente , Ian David Judd , Robert Bruce Nicholson , Mandy A Stevens
发明人： Carlos Francisco Fuente , Ian David Judd , Robert Bruce Nicholson , Mandy A Stevens
IPC分类号： G06F13/16
CPC分类号： G06F13/28
摘要： A copy engine (104) is provided as an interface between firmware (108) and memory space (106) for carrying out copy operations. The copy engine has a first register (202, 203) to point to a first address and a second register (204, 205) to point to a second address. One of the first and second addresses is a source address and one is a destination address for data to be copied. The copy engine (104) also has a control register (201). The control register (201) includes a count of the amount of memory space required by a copy operation, an indication of the direction of the copy operation from the first address to the second address or from the second address to the first address, and an indication of whether the first memory address is incremented or decremented. The copy engine (104) includes a locking mechanism for locking the copy engine (104) during a copy operation. The copy engine (104) also includes a serialization mechanism in which a write is made to control register (201) of zero count. If the copy engine (104) is locked, the write of zero count is retried until the existing copy operation has completed and then it will complete with no effect.
摘要翻译：提供复制引擎（104）作为固件（108）和存储器空间（106）之间的接口，用于执行复制操作。复制引擎具有指向第一地址的第一寄存器（202,203）和指向第二地址的第二寄存器（204,205）。第一和第二地址之一是源地址，一个是要复制的数据的目的地址。复制引擎（104）还具有控制寄存器（201）。控制寄存器（201）包括由复制操作所需的存储空间量的计数，从第一地址到第二地址或从第二地址到第一地址的复制操作的方向的指示，以及指示第一个存储器地址是递增还是递减。复印机（104）包括用于在复印操作期间锁定复印机（104）的锁定机构。复制引擎（104）还包括一个序列化机制，其中写入零计数的控制寄存器（201）。如果复制引擎（104）被锁定，则重试零计数，直到现有的复制操作完成，然后它将不起作用。

30. 发明申请

US20070101085A1 Copy engine and a method for data movement 失效
标题翻译：复制引擎和数据移动方法
公开(公告)号：US20070101085A1
公开(公告)日：2007-05-03
申请号：US11598311
申请日：2006-11-13
申请人： Carlos Francisco Fuente , Ian David Judd , Robert Bruce Nicholson , Mandy Stevens
发明人： Carlos Francisco Fuente , Ian David Judd , Robert Bruce Nicholson , Mandy Stevens
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F13/28
摘要： A copy engine (104) is provided as an interface between firmware (108) and memory space (106) for carrying out copy operations. The copy engine has a first register (202, 203) to point to a first address and a second register (204, 205) to point to a second address. One of the first and second addresses is a source address and one is a destination address for data to be copied. The copy engine (104) also has a control register (201). The control register (201) includes a count of the amount of memory space required by a copy operation, an indication of the direction of the copy operation from the first address to the second address or from the second address to the first address, and an indication of whether the first memory address is incremented or decremented. The copy engine (104) includes a locking mechanism for locking the copy engine (104) during a copy operation. The copy engine (104) also includes a serialisation mechanism in which a write is made to the control register (201) of zero count. If the copy engine (104) is locked, the write of zero count is retried until the existing copy operation has completed and then it will complete with no effect.
摘要翻译：提供复制引擎（104）作为固件（108）和存储器空间（106）之间的接口，用于执行复制操作。复制引擎具有指向第一地址的第一寄存器（202,203）和指向第二地址的第二寄存器（204,205）。第一和第二地址之一是源地址，一个是要复制的数据的目的地址。复制引擎（104）还具有控制寄存器（201）。控制寄存器（201）包括由复制操作所需的存储空间量的计数，从第一地址到第二地址或从第二地址到第一地址的复制操作的方向的指示，以及指示第一个存储器地址是递增还是递减。复印机（104）包括用于在复印操作期间锁定复印机（104）的锁定机构。复制引擎（104）还包括序列化机制，其中对计数的控制寄存器（201）进行写入。如果复制引擎（104）被锁定，则重试零计数，直到现有的复制操作完成，然后它将不起作用。

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