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    • 1. 发明授权
    • VLSI chip macro interface
    • VLSI芯片宏接口
    • US06467001B1
    • 2002-10-15
    • US09374222
    • 1999-08-13
    • Mandy Alexander GrayMichael J. PalmerIan David Judd
    • Mandy Alexander GrayMichael J. PalmerIan David Judd
    • G06F1336
    • H04L49/101
    • The present invention provides a method and a system for connecting together, in a VLSI chip, a plurality of macros which require data flow connections between each other. A simple standard interface is realised between all macros. Any number of macros can be connected together, also allowing concurrent transactions between 4 or more macros using a cross-bar switch. Each macro may be a master (capable of requesting connections), a slave (capable of receiving connections from a master) or both. The centralised inter-connect logic includes three major components: the cross-bar switch, which makes the connections between the macros, the address decoder, which determines which slave each master wishes to connect to and an arbiter, which arbitrates between the macros when two or more masters request a connection simultaneously.
    • 本发明提供了一种用于在VLSI芯片中将需要相互数据流连接的多个宏连接在一起的方法和系统。 所有宏之间实现简单的标准接口。 任何数量的宏都可以连接在一起,也允许使用交叉开关的4个或更多宏之间的并发事务。 每个宏可以是主(能够请求连接),从机(能够从主机接收连接)或两者。 集中式互连逻辑包括三个主要部分:交叉开关,它们使得宏之间的连接,地址解码器确定每个主机希望连接的从属和仲裁器,它们在宏之间进行仲裁 或更多的主人同时请求连接。
    • 5. 发明授权
    • System and method for detecting write errors in a storage device
    • 用于检测存储设备中写入错误的系统和方法
    • US07380198B2
    • 2008-05-27
    • US10839106
    • 2004-05-05
    • Ian David Judd
    • Ian David Judd
    • G11C29/00G11C7/00H03M13/00
    • G11B20/18G06F11/1076G06F2211/1059
    • A system for detecting write errors in a storage device is disclosed. The system comprises a storage device; within the storage device, means for storing one or more data blocks in a storage group, the storage group comprising the one or more data blocks and a check block, wherein the check block comprises one of the group of: a combination of the one or more data blocks of the storage group, a combination of one or more bits of a logical block address associated with the storage group, and a combination of one or more bits of a phase field that is updated each time the storage group is written; means for updating the check block each time the storage group is written; and means for detecting write errors by checking the check block.
    • 公开了一种用于检测存储装置中的写入错误的系统。 该系统包括存储装置; 在所述存储设备内,用于将一个或多个数据块存储在存储组中的装置,所述存储组包括所述一个或多个数据块和校验块,其中所述校验块包括以下组中的一个:所述一个或多个 存储组的更多数据块,与存储组相关联的逻辑块地址的一个或多个位的组合,以及每次存储组被写入时更新的相位字段的一个或多个位的组合; 每次存储组写入时更新检查块的装置; 以及用于通过检查检查块来检测写入错误的装置。
    • 6. 发明授权
    • Bypass circuit for bypassing host computer which are connected to
plurality of devices via two individual ports upon detecting lack of
communication at both ports
    • 旁路电路,用于在检测到两个端口上的通信不足时,经由两个单独端口连接到多个设备的主机
    • US6038618A
    • 2000-03-14
    • US907580
    • 1997-08-08
    • Reginald BeerPeter John DeaconIan David JuddNeil Morris
    • Reginald BeerPeter John DeaconIan David JuddNeil Morris
    • H04L12/437C06F11/22
    • H04L12/437
    • A data processing system comprises a host computer connected for the transfer of data to and from a plurality of data storage devices arranged in a string, the host computer including communication means comprising first and second ports connecting to first and second communication links, the first and second communication links being connected respectively to first and second data storage devices of said string. A bypassing means is provided between the first and second ports of the host system and the first and second data storage devices, the bypassing means being comprised of an independent bypass circuit on each of the first and second communication links between each of the first and second ports and the first and second data storage devices, the bypassing means being operable to bypass the host computer by connecting the first and second devices only when both of said independent bypass circuits detect a lack of data transfer on their respective links.
    • 一种数据处理系统包括连接到用于将数据传送到排列在一串中的多个数据存储设备的主计算机,该主计算机包括通信装置,该通信装置包括连接到第一和第二通信链路的第一和第二端口,第一和第二通信链路 第二通信链路分别连接到所述串的第一和第二数据存储设备。 旁路装置设置在主机系统的第一和第二端口与第一和第二数据存储装置之间,旁路装置包括在第一和第二通信链路中的每个第一和第二通信链路之间的独立旁路电路 端口和第一和第二数据存储设备,旁路装置可操作以仅在两个独立旁路电路检测到其各自链路上的数据传输不足时才通过连接第一和第二设备来绕过主计算机。