专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US08710916B2 Electronic circuit having shared leakage current reduction circuits 有权
标题翻译：具有共享泄漏电流降低电路的电子电路
公开(公告)号：US08710916B2
公开(公告)日：2014-04-29
申请号：US13020565
申请日：2011-02-03
申请人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell , Shayan Zhang
发明人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell , Shayan Zhang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K19/0008 , H03K19/0016
摘要： An electronic circuit includes a plurality of circuit blocks, a plurality of bias circuits, a switching circuit, and plurality of transistors. The plurality of circuit blocks each includes a high power terminal and a low power terminal. The switching circuit includes a plurality of switches for selectively coupling a bias circuit of the plurality of bias circuits to the low power terminal of a circuit block of the plurality of circuit blocks. Each bias circuit of the plurality of bias circuits is selectively couplable to the low power terminal of each of the plurality of circuit blocks. Each transistor of the plurality of transistors has a first current terminal coupled to a circuit ground terminal, and each transistor of the plurality of transistors has a control terminal for controlling the conductivity of the plurality of the transistors by a bias circuit of the plurality of bias circuits.
摘要翻译：电子电路包括多个电路块，多个偏置电路，开关电路和多个晶体管。多个电路块各自包括高功率端子和低功率端子。开关电路包括多个开关，用于将多个偏置电路的偏置电路选择性地耦合到多个电路块的电路块的低功率端子。多个偏置电路的每个偏置电路可以选择性地耦合到多个电路块中的每一个的低功率端子。多个晶体管的每个晶体管具有耦合到电路接地端子的第一电流端子，并且多个晶体管中的每个晶体管具有控制端子，用于通过多个偏置的偏置电路来控制多个晶体管的导电性电路。

22. 发明授权

US08566836B2 Multi-core system on chip 有权
标题翻译：多芯片系统芯片
公开(公告)号：US08566836B2
公开(公告)日：2013-10-22
申请号：US12618311
申请日：2009-11-13
申请人： Ravindraraj Ramaraju , David R. Bearden , William C. Moyer
发明人： Ravindraraj Ramaraju , David R. Bearden , William C. Moyer
IPC分类号： G06F9/46 , G06F7/38
CPC分类号： G06F9/5044 , Y02D10/22
摘要： A multi-core system on a chip (200) is described in which a speed information for each core (210, 220, 230, 240), such as the maximum operation speed (Fmax), is extracted and stored in a storage device, such as a device control registry (215), where it may be accessed and used by the operating system when allocating workload among the cores by selecting the fasted core (e.g, 210) to run any applications or tasks that can not be executed on a plurality of cores.
摘要翻译：描述了一种芯片上的多核系统（200），其中提取每个核心（210,220,230,240）的速度信息（如最大运行速度（Fmax））并将其存储在存储装置中，例如设备控制注册表（215），其中当通过选择禁止的核心（例如，210）来运行任何不能执行的应用程序或任务时，操作系统可以在操作系统之间分配工作负载时，访问和使用它们多个核心。

23. 发明申请

US20110191602A1 PROCESSOR WITH SELECTABLE LONGEVITY 审中-公开
标题翻译：具有可选择长度的处理器
公开(公告)号：US20110191602A1
公开(公告)日：2011-08-04
申请号：US12696633
申请日：2010-01-29
申请人： David R. Bearden , Ravindraraj Ramaraju , Peter P. Abramowitz , William C. Moyer
发明人： David R. Bearden , Ravindraraj Ramaraju , Peter P. Abramowitz , William C. Moyer
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A processor and method has at least one processor core for processing information and receives an operating voltage for powering circuitry of the processor. A selector receives a value indicative of a temperature within the processor and receives a value from a plurality of possible longevity values that each indicates a predetermined desired longevity of valid operation of the processor. An output provides an identifier that controls at least one of an operating voltage or an operating frequency of the processor, wherein the identifier provided is at least based on the value indicative of temperature and the predetermined desired longevity. A reliability storage device coupled to the selector stores the value from the plurality of possible longevity values that each indicates the predetermined desired longevity of valid operation of the processor.
摘要翻译：处理器和方法具有用于处理信息的至少一个处理器核心并且接收用于为处理器的电路供电的工作电压。选择器接收指示处理器内的温度的值，并从多个可能的寿命值接收值，每个可能的寿命值指示处理器的有效操作的预定期望寿命。输出提供控制处理器的操作电压或操作频率中的至少一个的标识符，其中提供的标识符至少基于指示温度和预定期望寿命的值。耦合到选择器的可靠性存储设备存储来自多个可能的寿命值的值，每个可能的寿命值指示处理器的有效操作的预定期望寿命。

24. 发明申请

US20100306302A1 TECHNIQUE FOR DETERMINING IF A LOGICAL SUM OF A FIRST OPERAND AND A SECOND OPERAND IS THE SAME AS A THIRD OPERAND 有权
标题翻译：如果第一个操作的逻辑关系和第二个操作与第三个操作相同，则用于确定的技术
公开(公告)号：US20100306302A1
公开(公告)日：2010-12-02
申请号：US12474451
申请日：2009-05-29
申请人： Ravindraraj Ramaraju , David R. Bearden , Klas M. Bruce , Michael D. Snyder
发明人： Ravindraraj Ramaraju , David R. Bearden , Klas M. Bruce , Michael D. Snyder
IPC分类号： G06F7/50 , G06F12/00 , G06F12/02
CPC分类号： G06F7/02 , G06F7/48 , G06F12/0864
摘要： A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.
摘要翻译：系统用于确定第一操作数和第二操作数的和是否与第三操作数相同，其中与第三操作数的比较具有可变长度。这在内容可寻址存储器（CAM）中特别有用，其中命中的可能性在集合的关联高速缓存中通常被改善，并允许CAM识别不同的事物。例如，条目可以是识别存储器的页面的一个长度，而另一个条目是不同的长度以标识存储器页面。通过参考以下描述和附图可以更好地理解这一点。

25. 发明申请

US20080222361A1 PIPELINED TAG AND INFORMATION ARRAY ACCESS WITH SPECULATIVE RETRIEVAL OF TAG THAT CORRESPONDS TO INFORMATION ACCESS 有权
标题翻译：管道标签和信息阵列访问与信息访问相关的标签的检索
公开(公告)号：US20080222361A1
公开(公告)日：2008-09-11
申请号：US11684529
申请日：2007-03-09
申请人： Ravindraraj Ramaraju , Ambica Ashok , David R. Bearden , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , Ambica Ashok , David R. Bearden , Prashant U. Kenkare
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , Y02D10/13
摘要： A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corresponding retrieval from an information array. In some exploitations, such a design may allow cycle times (and throughput) of a memory subsystem to more closely match demands of some processor and computation system architectures. In some cases, phased access can be described as pipelined tag and information array access, though strictly speaking, indexing into the information array need not depend on results of the tag array access. Our techniques seek to allow early (indeed speculative) retrieval from the tag array without delays that would otherwise be associated with calculation of an effective address eventually employed for a corresponding retrieval from the information array. Speculation can be resolved using the eventually calculated effective address or using separate functionality. In some embodiments, we use calculated effective addresses for way selection based on tags retrieved from the tag array.
摘要翻译：描述了一种高速缓存设计，其中对标签和信息数组的相应访问在时间上是相位的，并且其中从标签数组中检索（通常是推测性地）的标签，而不受随后用于从信息数组的相应检索的有效地址计算的益处。在一些开发中，这样的设计可以允许存储器子系统的周期时间（和吞吐量）更接近地匹配一些处理器和计算系统架构的需求。在某些情况下，分阶段访问可以被描述为流水线标签和信息数组访问，但严格来说，索引到信息数组不需要依赖于标签数组访问的结果。我们的技术旨在允许从标签数组中提前（确实是推测性的）检索，而不会延迟，否则将与从信息数组中相应检索最终采用的有效地址的计算相关联。可以使用最终计算的有效地址或使用单独的功能来解决投机。在一些实施例中，我们使用基于从标签阵列检索的标签的方法选择的计算的有效地址。

26. 发明授权

US07187205B2 Integrated circuit storage element having low power data retention and method therefor 有权
标题翻译：具有低功率数据保持的集成电路存储元件及其方法
公开(公告)号：US07187205B2
公开(公告)日：2007-03-06
申请号：US11065793
申请日：2005-02-25
申请人： Ravindraraj Ramaraju , David R. Bearden , Arthur R. Piejko
发明人： Ravindraraj Ramaraju , David R. Bearden , Arthur R. Piejko
IPC分类号： H03K19/0175
CPC分类号： H03K3/356008
摘要： A storage element (10) includes a first latch (12) and a second latch (14). The first latch (12) is coupled to a first power supply voltage terminal for receiving a first power supply voltage. The second latch (14) is coupled to a second power supply voltage terminal. The second power supply voltage terminal for receiving a second power supply voltage that is lower than the first power supply voltage. During a normal mode of operation, the second power supply voltage is not provided to the second latch. During a low power mode of operation data is transferred from the first latch to the second latch and the first latch is powered down. The data is retained by the second latch while in low power mode.
摘要翻译：存储元件（10）包括第一闩锁（12）和第二闩锁（14）。第一锁存器（12）耦合到第一电源电压端子，用于接收第一电源电压。第二锁存器（14）耦合到第二电源电压端子。所述第二电源电压端子用于接收低于所述第一电源电压的第二电源电压。在正常操作模式期间，第二电源电压不被提供给第二锁存器。在低功率操作模式期间，数据从第一锁存器传送到第二锁存器，并且第一锁存器掉电。在低功率模式下，数据由第二个锁存器保留。

27. 发明申请

US20110265090A1 MULTIPLE CORE DATA PROCESSOR WITH USAGE MONITORING 审中-公开
标题翻译：多核心数据处理器使用监控
公开(公告)号：US20110265090A1
公开(公告)日：2011-10-27
申请号：US12765534
申请日：2010-04-22
申请人： WILLIAM C. MOYER , Ravindraraj Ramaraju , David R. Bearden
发明人： WILLIAM C. MOYER , Ravindraraj Ramaraju , David R. Bearden
IPC分类号： G06F9/46 , G06F17/30
CPC分类号： G06F9/5027 , G06F1/3203 , G06F11/3423 , G06F11/3433 , G06F16/217 , G06F2209/508
摘要： A data processor with a plurality of processor cores. Accumulated usage information of each of the plurality of processor cores is stored in a storage device within the data processor, wherein the accumulated usage information is indicative of accumulated usage of each processor core of the plurality of processor cores. Accumulated usage information for a core of the plurality of processor cores is updated in response to a determined use of the core.
摘要翻译：具有多个处理器核心的数据处理器。多个处理器核心中的每一个的累积使用信息被存储在数据处理器内的存储设备中，其中累积的使用信息指示多个处理器核心的每个处理器核心的累积使用。响应于所确定的核心的使用，更新多个处理器核心的累积使用信息。

28. 发明授权

US07843218B1 Data latch with structural hold 有权
标题翻译：数据锁存结构保持
公开(公告)号：US07843218B1
公开(公告)日：2010-11-30
申请号：US12607657
申请日：2009-10-28
申请人： Ravindraraj Ramaraju , David R. Bearden , Cody B. Croxton , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , David R. Bearden , Cody B. Croxton , Prashant U. Kenkare
IPC分类号： H03K19/173
CPC分类号： G01R31/318541
摘要： A multiplexed data flip-flop circuit (500) is described in which a multiplexer (510) outputs functional or scan data, a master latch (520) generates a master latch output signal at a hold time under control of a master clock signal, a slave latch (540) generates a flip flop output signal at a launch time under control of a slave clock signal, clock generation circuitry (550) generates a second clock signal that has a DC state during a functional mode and has a switching state during a scan mode, and data propagation logic circuitry (564) uses the first and second clock signals to generate the master and slave clock signals during a scan mode to delay the launch time of the slave latch with respect to the hold time of the master latch.
摘要翻译：描述了多路复用数据触发器电路（500），其中复用器（510）输出功能或扫描数据，主锁存器（520）在主时钟信号的控制下在保持时间产生主锁存器输出信号，从锁存器（540）在从时钟信号的控制下在启动时产生触发器输出信号，时钟产生电路（550）产生在功能模式期间具有DC状态的第二时钟信号，并且在第一时钟信号期间具有开关状态扫描模式和数据传播逻辑电路（564）在扫描模式期间使用第一和第二时钟信号来产生主时钟信号和从时钟信号，以相对于主锁存器的保持时间延迟从锁存器的启动时间。

29. 发明申请

US20100207687A1 CIRCUIT FOR A LOW POWER MODE 有权
标题翻译：低功耗模式电路
公开(公告)号：US20100207687A1
公开(公告)日：2010-08-19
申请号：US12372997
申请日：2009-02-18
申请人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg
发明人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , G11C5/147
摘要： A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.
摘要翻译：电路具有第一晶体管，其具有耦合到第一电源电压端子的第一电流电极和耦合到虚拟电源电压节点的第二电流电极。第二晶体管具有耦合到第一电源电压端子的第一电流电极和耦合到虚拟电源电压节点的控制电极。第一负载具有输入并且具有耦合到第二晶体管的第二电流电极的输出。第三晶体管具有耦合到第一负载的输出的控制电极。第二负载具有耦合到第一电源电压端子的输入，并且具有耦合到第一晶体管的控制电极和第三晶体管的第一电流电极两者的输出。虚拟电源电压节点向在正常和困倦的操作模式之间交替的电路模块提供工作电压。

30. 发明授权

US07548103B2 Storage device having low power mode and methods thereof 有权
标题翻译：具有低功率模式的存储装置及其方法
公开(公告)号：US07548103B2
公开(公告)日：2009-06-16
申请号：US11553022
申请日：2006-10-26
申请人： Ravindraraj Ramaraju , David R. Bearden
发明人： Ravindraraj Ramaraju , David R. Bearden
IPC分类号： H03K3/00
CPC分类号： H03K3/35625 , H03K3/012 , H03K3/356156
摘要： A storage device and methods thereof are disclosed. The device includes a clock control module and a latch. During normal operation, the clock control module provides a periodic clock signal to a clock input of the latch, allowing the latch to operate normally. In a low power mode of operation, the clock control module provides a constant signal to the clock input of the latch so that the latch retains stored data during the low power mode of operation. The storage device can also include a power control module that provides a first power level to the latch in the normal mode of operation and a second power level during the second mode of operation.
摘要翻译：公开了一种存储装置及其方法。该装置包括时钟控制模块和锁存器。在正常操作期间，时钟控制模块向锁存器的时钟输入提供周期性的时钟信号，允许锁存器正常工作。在低功耗操作模式下，时钟控制模块向锁存器的时钟输入提供恒定的信号，使得锁存器在低功耗操作模式期间保持存储的数据。存储设备还可以包括功率控制模块，其在正常操作模式下向锁存器提供第一功率电平，并且在第二操作模式期间提供第二功率电平。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式