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21. 发明授权

US08443230B1 Methods and systems with transaction-level lockstep 有权
标题翻译：具有事务级锁步的方法和系统
公开(公告)号：US08443230B1
公开(公告)日：2013-05-14
申请号：US12969355
申请日：2010-12-15
申请人： Philip B. James-Roxby , Ralph D. Wittig , Brendan K. Bridgford , Robert M. McGee , Richard DeFelice
发明人： Philip B. James-Roxby , Ralph D. Wittig , Brendan K. Bridgford , Robert M. McGee , Richard DeFelice
IPC分类号： G06F11/00
CPC分类号： G06F11/1641 , G06F11/1683
摘要： Methods and systems for redundant operation of a first and second processor are provided. A set of instructions is executed in parallel on the first and second processors. In response to a first access transaction for a peripheral device being issued from execution of an instruction by the first processor, the first processor suspends operation. In response to the first access transaction being a write transaction, the write transaction is not issued to the peripheral device until the second processor executes the instruction and issues a second access transaction that is equal to the write transaction. In response to the first access transaction being a read transaction, the read transaction is not issued to the peripheral device until the second processor executes the instruction.
摘要翻译：提供了用于第一和第二处理器的冗余操作的方法和系统。一组指令在第一和第二处理器上并行执行。响应于由第一处理器执行指令而发出的用于外围设备的第一访问事务，第一处理器暂停操作。响应于作为写事务的第一访问事务，在第二处理器执行指令并发出等于写事务的第二访问事务之前，不向外围设备发出写事务。响应于作为读取事务的第一访问事务，在第二处理器执行指令之前，不向外围设备发出读取事务。

22. 发明授权

US08127262B1 Communicating state data between stages of pipelined packet processor 有权
标题翻译：在流水线分组处理器的阶段之间通信状态数据
公开(公告)号：US08127262B1
公开(公告)日：2012-02-28
申请号：US12337886
申请日：2008-12-18
申请人： Philip B. James-Roxby , Michael E. Attig
发明人： Philip B. James-Roxby , Michael E. Attig
IPC分类号： G06F17/50
CPC分类号： H04L47/2441
摘要： Approaches for generating a specification of a pipelined packet processor. A textual specification includes input and output packet formats, each specifying a format for each field in the packet and a plurality of actions for processing one or more fields of an input packet. Pipeline stages are determined from the actions in the textual specification, and each action is assigned to one of the pipeline stages. A shared variable is determined that is accessed by actions in at least two stages. An action in an initial stage writes the shared variable, an action in a last stage reads the shared variable. A hardware description is generated including the pipeline stages and assigned actions, a respective first-in-first-out queue between each adjacent pair of pipeline stages, a respective register for transferring the shared variable between each adjacent pair of the pipeline stages, and control logic for writing to and reading from each respective register.
摘要翻译：用于生成流水线分组处理器的规范的方法。文本规范包括输入和输出分组格式，每个格式指定分组中的每个字段的格式以及用于处理输入分组的一个或多个字段的多个动作。流水线阶段由文本规范中的动作确定，每个动作都分配给其中一个流水线阶段。确定通过至少两个阶段的动作访问的共享变量。一个初始阶段的动作写入共享变量，最后一个动作读取共享变量。产生包括流水线级和分配动作的硬件描述，每个相邻的流水线级对之间的相应先进先出队列，用于在每个相邻的一对流水线级之间传送共享变量的相应寄存器和控制用于写入和读取每个相应寄存器的逻辑。

23. 发明授权

US08065130B1 Method for message processing on a programmable logic device 有权
标题翻译：在可编程逻辑器件上进行消息处理的方法
公开(公告)号：US08065130B1
公开(公告)日：2011-11-22
申请号：US12465247
申请日：2009-05-13
申请人： Gordon J. Brebner , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni
发明人： Gordon J. Brebner , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , H04L45/60
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to the integrated circuit for storage in the memory. The memory is accessed with the plurality of threads to concurrently process a plurality of the messages.
摘要翻译：描述了用于实现使用集成电路的消息处理系统的可编程架构。在一个示例中，集成电路的可配置逻辑被配置为具有多个线程电路和存储器。消息被接收到集成电路以存储在存储器中。利用多个线程来访问存储器以同时处理多个消息。

24. 发明授权

US07784014B1 Generation of a specification of a network packet processor 有权
标题翻译：生成网络包处理器的规范
公开(公告)号：US07784014B1
公开(公告)日：2010-08-24
申请号：US11799897
申请日：2007-05-03
申请人： Gordon J. Brebner , Christopher E. Neely , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni , Michael A. Baxter , Henry E. Styles , Graham F. Schelle
发明人： Gordon J. Brebner , Christopher E. Neely , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni , Michael A. Baxter , Henry E. Styles , Graham F. Schelle
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method is provided for generating a hardware description language (HDL) specification of a network packet processor from a textual language specification of the processing of network packets by the processor. The processor includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The textual language specification identifies the ports of the processor. The textual language specification includes formats for the type or types of the incoming and outgoing network packets. Each format includes the fields of the type of network packet. The textual language specification includes a procedure for each input port and for each type of incoming network packet received at the input port. Each procedure includes one or more actions for modifying the fields of a type of network packet as a function of state data and/or the fields of the type of network packet.
摘要翻译：提供了一种从处理器对网络分组的处理的文本语言规范生成网络分组处理器的硬件描述语言（HDL）规范的方法。处理器包括前视级，操作级，插入/移除级和交错级。文本语言规范识别处理器的端口。文本语言规范包括进出网络数据包的类型或类型的格式。每个格式包括网络包类型的字段。文本语言规范包括每个输入端口和在输入端口接收的每种类型的传入网络分组的过程。每个过程包括用于根据状态数据和/或网络分组类型的字段修改网络分组类型的字段的一个或多个动作。

25. 发明授权

US07698449B1 Method and apparatus for configuring a processor embedded in an integrated circuit for use as a logic element 有权
标题翻译：用于配置嵌入在集成电路中用作逻辑元件的处理器的方法和装置
公开(公告)号：US07698449B1
公开(公告)日：2010-04-13
申请号：US11064148
申请日：2005-02-23
申请人： Eric R. Keller , Philip B. James-Roxby
发明人： Eric R. Keller , Philip B. James-Roxby
IPC分类号： G06F15/163
CPC分类号： G06F15/7867 , G06F9/30058 , G06F9/30072 , G06F9/30116 , G06F9/30134 , G06F9/325 , G06F9/383
摘要： Method and apparatus for configuring a processor embedded in an integrated circuit for use as a logic element is described. In one example, a processing apparatus in an integrated circuit includes a point-to-point data streaming interface and arithmetic logic unit (ALU) circuitry. The ALU circuitry includes at least one input port in communication with the point-to-point data streaming interface. The processor may also include a register file and multiplexer logic. The multiplexer logic is configured to selectively couple the register file and the point-to-point streaming interface to the at least one input port of the ALU circuitry.
摘要翻译：描述用于配置嵌入在用于逻辑元件的集成电路中的处理器的方法和装置。在一个示例中，集成电路中的处理装置包括点到点数据流接口和算术逻辑单元（ALU）电路。 ALU电路包括与点对点数据流接口通信的至少一个输入端口。处理器还可以包括寄存器文件和多路复用器逻辑。多路复用器逻辑被配置为选择性地将寄存器文件和点对点流接口耦合到ALU电路的至少一个输入端口。

26. 发明授权

US07653895B1 Memory arrangement for message processing by a plurality of threads 有权
标题翻译：用于多个线程的消息处理的存储器布置
公开(公告)号：US07653895B1
公开(公告)日：2010-01-26
申请号：US11336211
申请日：2006-01-20
申请人： Philip B. James-Roxby , Eric R. Keller
发明人： Philip B. James-Roxby , Eric R. Keller
IPC分类号： G06F9/44
CPC分类号： H04L69/12
摘要： Various approaches for preparing a system for multi-thread processing of messages are disclosed. In one approach, respective portions of a message accessed by a plurality of threads are determined from a high-level language programming specification of the threads. A plurality of input elements are generated and respectively coupled to the plurality of threads. Each input element is configured to select from the message received by the input element the portion of the message accessed by the respective thread and provide each selected portion to the respective thread. A plurality of output elements are generated and configured with storage for data output by a respective thread. From a definition of an output message, a concentrator element is generated and is configured to read data from the output elements and assemble the data into an output message according to the definition of the output message.
摘要翻译：公开了用于准备用于消息的多线程处理的系统的各种方法。在一种方法中，由线程的高级语言编程规范确定由多个线程访问的消息的相应部分。生成多个输入元件并分别耦合到多个线程。每个输入元件被配置为从由输入元件接收的消息中选择由相应线程访问的消息的部分，并将每个选择的部分提供给相应的线程。生成多个输出元件并配置有用于由相应线程输出的数据的存储器。根据输出消息的定义，生成集中器元件，并且被配置为从输出元件读取数据，并根据输出消息的定义将数据组合成输出消息。

27. 发明授权

US08479042B1 Transaction-level lockstep 有权
标题翻译：事务级锁定步骤
公开(公告)号：US08479042B1
公开(公告)日：2013-07-02
申请号：US12916904
申请日：2010-11-01
申请人： Philip B. James-Roxby , Ralph D. Wittig
发明人： Philip B. James-Roxby , Ralph D. Wittig
IPC分类号： G06F11/00
CPC分类号： G06F11/1641 , G06F11/1683
摘要： An embodiment of a method for a high-assurance operation is disclosed. For this embodiment of the method, a first processor and a second processor are clocked for lockstep operation. A first physical address and a first transaction request are provided to a shared bus from the first processor. A second physical address and a second transaction request are provided to the shared bus from the second processor. The first physical address, the first transaction request, the second physical address, and the second transaction request are passed to a proxy device coupled to the shared bus. The first processor and the second processor are proxy served by the proxy device including generation of a third transaction request and a third physical address by the proxy device.
摘要翻译：公开了一种用于高保证操作的方法的实施例。对于该方法的该实施例，第一处理器和第二处理器被计时以进行锁步操作。从第一处理器向共享总线提供第一物理地址和第一事务请求。从第二处理器向共享总线提供第二物理地址和第二事务请求。第一物理地址，第一事务请求，第二物理地址和第二事务请求被传递到耦合到共享总线的代理设备。第一处理器和第二处理器是代理服务的代理服务器，包括由代理设备产生第三事务请求和第三物理地址。

28. 发明授权

US07949793B1 Method and apparatus for providing an interface between a programmable circuit and a processor 有权
标题翻译：用于在可编程电路和处理器之间提供接口的方法和装置
公开(公告)号：US07949793B1
公开(公告)日：2011-05-24
申请号：US11228938
申请日：2005-09-16
申请人： Philip B. James-Roxby , Gordon J. Brebner
发明人： Philip B. James-Roxby , Gordon J. Brebner
IPC分类号： G06F3/00
CPC分类号： G06F13/4265
摘要： Method and apparatus for interfacing a programmable circuit and a processor is described. In one example, data output from the programmable circuit is packetized to form at least one packet. The at least one packet is provided to the processor via a streaming interface. The data is extracted from the at least one packet. A function is executed on the processor using the data as parametric input. Return data is then packetized by the function in response to the parametric input to produce at least one return packet. The at least one return packet is send towards the programmable circuit via the streaming interface. The return data is extracted from the at least one return packet and provided to the programmable circuit.
摘要翻译：描述了用于连接可编程电路和处理器的方法和装置。在一个示例中，从可编程电路输出的数据被打包以形成至少一个分组。经由流式接口将至少一个分组提供给处理器。从至少一个分组提取数据。使用数据作为参数输入在处理器上执行一个功能。然后，响应于参数输入，返回数据被功能打包以产生至少一个返回分组。至少一个返回包经由流式接口发送到可编程电路。返回数据从至少一个返回包中提取并提供给可编程电路。

29. 发明授权

US07788402B1 Circuit for modification of a network packet by insertion or removal of a data segment 有权
标题翻译：通过插入或删除数据段来修改网络包的电路
公开(公告)号：US07788402B1
公开(公告)日：2010-08-31
申请号：US11799898
申请日：2007-05-03
申请人： Eric R. Keller , Graham F. Schelle , Philip B. James-Roxby
发明人： Eric R. Keller , Graham F. Schelle , Philip B. James-Roxby
IPC分类号： G06F15/16 , H04L12/56 , H04L12/28 , H04J3/12
CPC分类号： H04L69/08
摘要： A state machine circuit converts a first network packet into a second network packet according to modification actions from a textual language specification. Each modification action is either an insertion action inserting a data segment or a removal action removing a data segment. Each state corresponds to a pairing of a first data word from the first packet and a second data word from the second packet. Each state selects the data units of the second data word from the data segment of each insertion action and the data units of both the first and a prior data word. Each state specifies one or more next states including the state corresponding to the pairing of either the first or a next data word after the first data word in the first sequence and either the second or a next data word after the second data word in the second sequence.
摘要翻译：状态机电路根据来自文本语言规范的修改动作将第一网络分组转换成第二网络分组。每个修改操作是插入操作插入数据段或删除操作删除数据段。每个状态对应于来自第一分组的第一数据字和来自第二分组的第二数据字的配对。每个状态从每个插入动作的数据段和第一和先前数据字的数据单元中选择第二数据字的数据单元。每个状态指定一个或多个下一状态，包括与第一序列中的第一数据字之后的第一或下一个数据字的配对相对应的状态，以及在第二序列中的第二数据字之后的第二或下一数据字序列。

30. 发明授权

US07770179B1 Method and apparatus for multithreading on a programmable logic device 有权
标题翻译：用于可编程逻辑器件上多线程的方法和装置
公开(公告)号：US07770179B1
公开(公告)日：2010-08-03
申请号：US10769330
申请日：2004-01-30
申请人： Philip B. James-Roxby , Gordon J. Brebner , Eric R. Keller , Chidamber R. Kulkarni
发明人： Philip B. James-Roxby , Gordon J. Brebner , Eric R. Keller , Chidamber R. Kulkarni
IPC分类号： G06F9/46 , G06F17/50
CPC分类号： G06F17/5054
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of the integrated circuit is configured to have a plurality of thread circuits and an interconnection topology amongst the plurality of thread circuits. Messages are concurrently processed using the plurality of thread circuits. Operation of at least one thread circuit of the plurality of thread circuits is controlled in accordance with control data received via the interconnection topology from at least one other thread circuit of the plurality of thread circuits.
摘要翻译：描述了用于实现使用集成电路的消息处理系统的可编程架构。在一个示例中，集成电路的可配置逻辑被配置为在多个线程电路之间具有多个线程电路和互连拓扑。使用多个线程电路同时处理消息。根据从多个线程电路的至少一个其它线程电路经由互连拓扑接收的控制数据来控制多个线程电路中的至少一个线程电路的操作。

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