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21. 发明申请

US20130293292A1 INTERLAYER COMMUNICATIONS FOR 3D INTEGRATED CIRCUIT STACK 有权
公开(公告)号：US20130293292A1
公开(公告)日：2013-11-07
申请号：US13976562
申请日：2011-09-30
申请人： Guido Droege , Niklas Linkewitsch , Andre Schaefer
发明人： Guido Droege , Niklas Linkewitsch , Andre Schaefer
IPC分类号： H01L23/522
CPC分类号： H01L25/0657 , G11C5/04 , G11C5/063 , G11C7/1057 , G11C7/1084 , H01L23/481 , H01L23/5223 , H01L23/642 , H01L2223/6622 , H01L2224/16145 , H01L2225/06513 , H01L2225/06544
摘要： Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.

22. 发明授权

US08547769B2 Energy efficient power distribution for 3D integrated circuit stack 有权
标题翻译：用于3D集成电路堆栈的节能配电
公开(公告)号：US08547769B2
公开(公告)日：2013-10-01
申请号：US13077359
申请日：2011-03-31
申请人： Ruchir Saraswat , Andre Schaefer , Supriyanto Supriyanto
发明人： Ruchir Saraswat , Andre Schaefer , Supriyanto Supriyanto
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G06F1/3275 , G06F1/3287 , G11C5/02 , H01L23/481 , H01L23/5286 , H01L25/0657 , H01L25/18 , H01L2225/06541 , H01L2924/0002 , Y02D10/14 , Y02D10/171 , H01L2924/00
摘要： Multiple dies can be stacked in what are commonly referred to as three-dimensional modules (or “stacks”) with interconnections between the dies, resulting in an IC module with increased circuit component capacity. Such structures can result in lower parasitics for charge transport to different components throughout the various different layers. In some embodiments, the present invention provides efficient power distribution approaches for supplying power to components in the different layers. For example, voltage levels for global supply rails may be increased to reduce required current densities for a given power objective.
摘要翻译：多个管芯可以堆叠在通常称为管芯之间的互连的三维模块（或“堆叠”）中，导致具有增加的电路部件容量的IC模块。这种结构可以导致电荷传输到各种不同层中不同组分的较低的寄生效应。在一些实施例中，本发明提供了用于向不同层中的部件供电的有效功率分配方法。例如，可以增加全球电源轨的电压电平，以减少给定电力目标的所需电流密度。

23. 发明授权

US08321719B2 Efficient clocking scheme for a bidirectional data link 有权
标题翻译：双向数据链路的高效计时方案
公开(公告)号：US08321719B2
公开(公告)日：2012-11-27
申请号：US12567701
申请日：2009-09-25
申请人： Andre Schaefer
发明人： Andre Schaefer
IPC分类号： G06F1/04 , G06F1/12 , G06F5/06
CPC分类号： G06F13/1689 , G11C7/1066 , G11C7/222
摘要： A method for communication via a bidirectional data link between a processing device and a memory device. The memory device includes a clock source to generate a clock signal for driving a latching at the memory device of data to and/or from the bidirectional data link. The memory device provides the clock signal to the processing device for driving a latching at the processing device of data to and/or from the bidirectional data link.
摘要翻译：一种用于通过处理设备和存储设备之间的双向数据链路进行通信的方法。存储器件包括时钟源，用于产生时钟信号，用于驱动在存储器件处的数据到和/或来自双向数据链路的锁存。存储装置向处理装置提供时钟信号，用于驱动处理装置处的数据到和/或来自双向数据链路的锁存。

24. 发明授权

US07180805B2 Differental current source for generating DRAM refresh signal 有权
标题翻译：用于产生DRAM刷新信号的不同电流源
公开(公告)号：US07180805B2
公开(公告)日：2007-02-20
申请号：US10386147
申请日：2003-03-11
申请人： Joachim Schnabel , Andre Schaefer
发明人： Joachim Schnabel , Andre Schaefer
IPC分类号： G11C7/00
CPC分类号： G11C7/04 , G11C11/406 , H03K3/0231
摘要： A circuit for generating a refresh signal for a memory cell of a semiconductor memory includes a capacitor and a differential current source for providing a charging current to the capacitor. The differential current source includes a temperature-dependent and a temperature-independent current source connected such that the charging current is proportional to a difference between a temperature-dependent current and a temperature-independent current. A comparator a voltage at a capacitor terminal and a reference voltage. The comparator generates a refresh signal when capacitor voltage exceeds the reference voltage.
摘要翻译：用于产生半导体存储器的存储单元的刷新信号的电路包括用于向电容器提供充电电流的电容器和差动电流源。差分电流源包括温度依赖性和独立于温度的电流源，其连接使得充电电流与温度相关电流和与温度无关的电流之间的差成比例。比较器电容端子的电压和参考电压。当电容器电压超过参考电压时，比较器产生刷新信号。

25. 发明授权

US08971087B2 Stacked memory with interface providing offset interconnects 有权
标题翻译：具有提供偏移互连的接口的堆叠存储器
公开(公告)号：US08971087B2
公开(公告)日：2015-03-03
申请号：US13997148
申请日：2011-12-02
申请人： Pete Vogt , Andre Schaefer , Warren Morrow , John Halbert , Jin Kim , Kenneth Shoemaker
发明人： Pete Vogt , Andre Schaefer , Warren Morrow , John Halbert , Jin Kim , Kenneth Shoemaker
IPC分类号： G11C5/06 , H01L27/108 , H01L25/065 , H01L23/48 , H01L23/00
CPC分类号： H01L25/0657 , G11C5/06 , H01L23/481 , H01L24/16 , H01L27/108 , H01L27/10882 , H01L27/10897 , H01L2224/16146 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541
摘要： Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.
摘要翻译：用于具有提供偏移互连的接口的堆叠存储器的操作的动态操作。存储器件的实施例包括与系统元件耦合的系统元件和存储器堆栈，存储器堆栈包括一个或多个存储器管芯层。每个存储器管芯层包括第一面和第二面，每个存储管芯层的第二面包括用于将存储管芯层的数据接口引脚与耦合元件的第一面的数据接口引脚耦合的接口。每个存储器管芯层的接口包括在存储管芯层的每个数据接口引脚和耦合元件的数据接口引脚的相应数据接口引脚之间提供偏移的连接。

26. 发明申请

US20150003181A1 POWER MANAGEMENT IN MULTI-DIE ASSEMBLIES 有权
标题翻译：多模组件电源管理
公开(公告)号：US20150003181A1
公开(公告)日：2015-01-01
申请号：US13927227
申请日：2013-06-26
申请人： Guido Droege , Andre Schaefer , Uwe Zillmann
发明人： Guido Droege , Andre Schaefer , Uwe Zillmann
IPC分类号： G11C5/14
CPC分类号： H02J1/00 , G05F1/618 , G11C5/025 , G11C5/14 , G11C5/147 , G11C7/00 , H01L2924/19042 , H01L2924/19104 , H02M1/088
摘要： An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.
摘要翻译：诸如异种装置的装置至少包括第一模具和第二模具。该装置还包括第一电感元件，第二电感元件和开关控制电路。开关控制电路设置在第一管芯中。开关控制电路控制通过第一电感元件的电流以产生第一电压。第一个电压为第一个模具供电。第二电感元件耦合到第一电感元件。第二电感元件产生第二电压以对第二管芯供电。第一模具和第二模具可以根据不同的技术制造，并且其中第一模具和第二模具耐受不同的最大电压。第一电压的大小可以大于第二电压的幅度。

27. 发明申请

US20140185392A1 MEMORY SENSE AMPLIFIER VOLTAGE MODULATION 有权
标题翻译：内存感测放大器电压调制
公开(公告)号：US20140185392A1
公开(公告)日：2014-07-03
申请号：US13728749
申请日：2012-12-27
申请人： Andre Schaefer
发明人： Andre Schaefer
IPC分类号： G11C7/08
CPC分类号： G11C7/08 , G11C11/4074 , G11C11/4091
摘要： Memory sense amplifier voltage modulation. An embodiment of a an apparatus includes a memory including a sense amplifier; a first node for an high voltage rail for the sense amplifier and a second node for a low voltage rail for the sense amplifier; one or more elements to provide a first voltage to the first node and a second voltage to the second node; and a voltage control engine to control the one or more elements, where the voltage control engine is to independently set a value of the first voltage and a value of the second voltage over time.
摘要翻译：存储读出放大器电压调制。一种装置的实施例包括：存储器，包括读出放大器; 用于读出放大器的高电压轨的第一节点和用于读出放大器的低电压轨的第二节点; 向所述第一节点提供第一电压的一个或多个元件，以及向所述第二节点提供第二电压的一个或多个元件; 以及电压控制引擎，用于控制所述一个或多个元件，其中所述电压控制引擎将独立地设置所述第一电压的值和所述第二电压随时间的值。

28. 发明申请

US20140006700A1 CONFIGURATION FOR POWER REDUCTION IN DRAM 有权
标题翻译： DRAM中功率降低配置
公开(公告)号：US20140006700A1
公开(公告)日：2014-01-02
申请号：US13536724
申请日：2012-06-28
申请人： Andre Schaefer , John B. Halbert
发明人： Andre Schaefer , John B. Halbert
IPC分类号： G06F12/00 , G11C5/14
CPC分类号： G11C11/4074 , G06F1/3275 , G11C8/08 , G11C8/14 , G11C11/4045 , G11C11/4085 , Y02D10/14
摘要： Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline drivers. The logic may partition a page of the apparatus to reduce power consumed through activation of the disabled ones of the number of segment wordlines. Other embodiments may be disclosed.
摘要翻译：公开的实施例可以包括具有能够选择性地禁用多个段字线驱动器中的一个的逻辑的段字线的装置。逻辑可以划分设备的页面，以通过激活段数字段线路中的禁用的一个来减少消耗的功率。可以公开其他实施例。

29. 发明申请

US20130279276A1 SEPARATE MICROCHANNEL VOLTAGE DOMAINS IN STACKED MEMORY ARCHITECTURE 有权
标题翻译：堆叠式存储器架构中的单独微通道电压域
公开(公告)号：US20130279276A1
公开(公告)日：2013-10-24
申请号：US13977404
申请日：2011-12-23
申请人： Andre Schaefer
发明人： Andre Schaefer
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C5/025 , G11C5/147 , G11C11/4074 , H01L25/0657 , H01L25/18 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2924/15311 , H01L2924/00012 , H01L2924/00
摘要： Separate microchannel voltage domains in a stacked memory architecture An embodiment of a memory device includes a memory stack including one or more coupled memory dies, wherein a first memory die of the memory stack includes multiple microchannels, and a logic chip coupled with the memory stack, the logic chip including a memory controller. Each of the microchannels includes a separate voltage domain, and a voltage level is controlled for each of the plurality of microchannels.
摘要翻译：在堆叠式存储器架构中的分离的微通道电压域存储器件的一个实施例包括一个包括一个或多个耦合的存储器管芯的存储器堆栈，其中存储器堆叠的第一存储器管芯包括多个微通道，以及与存储堆栈耦合的逻辑芯片，逻辑芯片包括存储器控制器。每个微通道包括单独的电压域，并且为多个微通道中的每一个控制电压电平。

30. 发明授权

US07321240B2 Driver circuit for binary signals 有权
标题翻译：二进制信号驱动电路
公开(公告)号：US07321240B2
公开(公告)日：2008-01-22
申请号：US11316379
申请日：2005-12-22
申请人： Andre Schaefer
发明人： Andre Schaefer
IPC分类号： H03K19/0175
CPC分类号： H03K17/162 , H03K17/08122
摘要： The invention relates to a driver circuit for binary signals, said circuit having two branch circuits which are connected in parallel with one another between an input node and an output node, the first of which branch circuits contains an output stage which, in response to the first binary value of a binary signal that is applied to the input node, connects the output node to a first logic potential via a first nonreactive resistor, and the second of which branch circuits contains an output stage which, in response to the second binary value of the binary signal that is applied to the input node, connects the output node to a second logic potential via a second nonreactive resistor. According to the invention, the driver circuit contains a duty ratio control device for setting the signal propagation time from the input node to the output stage of one branch circuit relative to the signal propagation time from the input node to the output stage of the other branch circuit.
摘要翻译：本发明涉及一种用于二进制信号的驱动电路，所述电路具有两个分支电路，它们在输入节点和输出节点之间彼此并联连接，其中第一支路电路包含输出级，响应于施加到输入节点的二进制信号的第一二进制值经由第一非反应电阻将输出节点连接到第一逻辑电位，其中第二二进制值包括输出级，响应于第二二进制值施加到输入节点的二进制信号通过第二非反应电阻将输出节点连接到第二逻辑电位。根据本发明，驱动电路包含占空比控制装置，用于相对于从另一分支的输入节点到输出级的信号传播时间，设定从一输入节点到一分支电路的输出级的信号传播时间电路。

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