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21. 发明申请

US20090172439A1 SYSTEM AND METHOD FOR FAST PLATFORM HIBERNATE AND RESUME 有权
标题翻译：快速平台自由和恢复的系统和方法
公开(公告)号：US20090172439A1
公开(公告)日：2009-07-02
申请号：US11965948
申请日：2007-12-28
申请人： Barnes Cooper , Faraz A. Siddiqi
发明人： Barnes Cooper , Faraz A. Siddiqi
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： In some embodiments, an apparatus includes processor cores, a smaller non-volatile memory, a larger non-volatile memory to hold an operating system, programs, and data for use by the processor cores. The apparatus also includes volatile memory to act as system memory for the processor cores, and power management logic to control at least some aspects of power management. In response to a power state change command, a system context is stored in the smaller non-volatile memory followed by the volatile memory losing power, and in response to a resume command, the volatile memory receives power and receives at least a portion of the system context from the smaller non-volatile memory. Other embodiments are described.
摘要翻译：在一些实施例中，装置包括处理器核，更小的非易失性存储器，用于保存操作系统，程序和数据的更大的非易失性存储器以供处理器核心使用。该装置还包括作为用于处理器核的系统存储器的易失性存储器，以及功率管理逻辑以控制功率管理的至少一些方面。响应于电源状态改变命令，系统上下文存储在较小的非易失性存储器中，随后易失性存储器丢失电力，并且响应于恢复命令，易失性存储器接收电力并接收至少一部分系统上下文从较小的非易失性存储器。描述其他实施例。

22. 发明申请

US20080162866A1 Apparatus and method for fast and secure memory context switching 审中-公开
标题翻译：用于快速和安全的存储器上下文切换的装置和方法
公开(公告)号：US20080162866A1
公开(公告)日：2008-07-03
申请号：US11648455
申请日：2006-12-28
申请人： Faraz A. Siddiqi , Kirk Brannock
发明人： Faraz A. Siddiqi , Kirk Brannock
IPC分类号： G06F12/06
CPC分类号： G06F9/45537
摘要： An apparatus comprising a memory controller including therein a configuration register, a communication channel coupled to the memory controller, and first and second memory partitions coupled to the communication channel, wherein configuration parameters in the configuration register are set so that the memory controller recognizes one partition at a time. A process comprising setting configuration parameters in a configuration register of a memory controller so that the memory controller recognizes a first memory partition coupled to the memory controller by a communication channel instead of a second memory partition coupled to the memory controller by the communication channel and re-setting the configuration parameters so that the memory controller recognizes the second memory partition instead of the first memory partition.
摘要翻译：一种装置，包括存储器控制器，其中包括配置寄存器，耦合到存储器控制器的通信信道以及耦合到通信信道的第一和第二存储器分区，其中配置寄存器中的配置参数被设置为使得存储器控制器识别一个分区一次一种过程，包括将配置参数设置在存储器控制器的配置寄存器中，使得存储器控制器通过通信信道识别耦合到存储器控制器的第一存储器分区，而不是通过通信信道而与存储器控制器耦合的第二存储器分区 - 设置配置参数，使得存储器控制器识别第二存储器分区而不是第一存储器分区。

23. 发明授权

US06704840B2 Computer system and method of computer initialization with caching of option BIOS 失效
标题翻译：计算机系统和计算机初始化方法，具有选项BIOS的缓存
公开(公告)号：US06704840B2
公开(公告)日：2004-03-09
申请号：US09883401
申请日：2001-06-19
申请人： Rejeev K. Nalawadi , Faraz A. Siddiqi
发明人： Rejeev K. Nalawadi , Faraz A. Siddiqi
IPC分类号： G06F1300
CPC分类号： G06F9/4401 , G06F12/0802
摘要： A computer system and method for computer initialization with caching includes enabling at least one cache memory and then copying an option basic input/output system (BIOS) from a first memory to a Programmable Attribute Map (PAM) main memory area, the copying including executing a cache-line fill to the at least one cache memory. Initialization is then performed by providing control to the option BIOS, the execution being performed substantially from the at least one cache memory. Processor Memory Type Range Registers (MTRRs) for the PAM memory area may be programmed as write-back. The at least one cache memory may be at least one of level 1 (L1) and level 2 (L2) processor cache memories. The first memory may be a flash memory or a ROM Read Only Memory (ROM). The at least one cache memory may be flushed upon completion of the option BIOS execution.
摘要翻译：一种用于具有缓存的计算机初始化的计算机系统和方法，包括启用至少一个高速缓存存储器，然后将选项基本输入/输出系统（BIOS）从第一存储器复制到可编程属性映射（PAM）主存储器区域，所述复制包括执行高速缓存行填充到所述至少一个高速缓冲存储器。然后通过向选项BIOS提供控制来执行初始化，该执行基本上从至少一个高速缓冲存储器执行。 PAM存储器区域的处理器存储器类型范围寄存器（MTRR）可以被编程为回写。至少一个高速缓存存储器可以是级别1（L1）和级别2（L2）处理器高速缓存存储器中的至少一个。第一存储器可以是闪存或ROM只读存储器（ROM）。完成选项BIOS执行时，可以刷新至少一个高速缓冲存储器。

24. 发明申请

US20140337918A1 CONTEXT BASED SWITCHING TO A SECURE OPERATING SYSTEM ENVIRONMENT 审中-公开
标题翻译：基于上下文的切换到安全的操作系统环境
公开(公告)号：US20140337918A1
公开(公告)日：2014-11-13
申请号：US13995555
申请日：2013-03-14
申请人： Faraz A. Siddiqi , Jasmeet Chhabra
发明人： Faraz A. Siddiqi , Jasmeet Chhabra
IPC分类号： H04L29/06 , G06F21/56
CPC分类号： H04L63/083 , G06F21/56 , G06F21/567 , G06F21/57 , G06F21/572 , G06F21/6245 , G06F21/6272 , G06F2221/2129 , H04L63/1433
摘要： Generally, this disclosure provides devices, systems, methods and computer readable media for context based switching to a secure OS environment including cloud based data synchronization and filtration. The device may include a storage controller to provide access to the secure OS stored in an initially provisioned state; a context determination module to monitor web site access, classify a transaction between the device and the website and identify a match between the web site and a list of web sites associated with secure OS operation or a match between the transaction classification and a list of transaction types associated with secure OS operation; and an OS switching module to switch from a main OS to the secure OS in response to the identified match. The switch may include updating state data associated with the secure OS, the state data received from a secure cloud-based data synchronization server.
摘要翻译：通常，本公开提供了用于基于上下文的切换到包括基于云的数据同步和过滤的安全OS环境的设备，系统，方法和计算机可读介质。设备可以包括存储控制器，以提供对以初始提供的状态存储的安全OS的访问; 上下文确定模块，用于监视网站访问，对设备和网站之间的交易进行分类，并且识别网站与与安全OS操作相关联的网站列表之间的匹配或交易分类与交易列表之间的匹配与安全操作系统操作相关联的类型; 以及OS切换模块，用于响应于所识别的匹配从主OS切换到安全OS。交换机可以包括更新与安全OS相关联的状态数据，从基于安全云的数据同步服务器接收的状态数据。

25. 发明申请

US20140189198A1 MEMORY ALLOCATION FOR FAST PLATFORM HIBERNATION AND RESUMPTION OF COMPUTING SYSTEMS 有权
标题翻译：快速平台自动记录分配和计算系统恢复
公开(公告)号：US20140189198A1
公开(公告)日：2014-07-03
申请号：US13730575
申请日：2012-12-28
申请人： Faraz A. Siddiqi , Francis R. Corrado , Barnes Cooper
发明人： Faraz A. Siddiqi , Francis R. Corrado , Barnes Cooper
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0638 , G06F12/0871 , G06F2212/1028 , Y02D10/13
摘要： Memory allocation for fast platform hibernation and resumption of computing systems. An embodiment of an apparatus includes logic at least partially implemented in hardware, the logic to: dynamically allocate at least a first portion of a nonvolatile memory; in response to a command to enter the apparatus into a standby state, the logic to store at least a portion of a context data from a volatile memory to the dynamically allocated first portion of the nonvolatile memory; and in response to a resumption of operation of the apparatus, the logic to copy at least the portion of the context data from the first portion of the nonvolatile memory to the volatile memory, and to reclaim the first portion of the nonvolatile memory for dynamic allocation.
摘要翻译：快速平台休眠和恢复计算系统的内存分配。装置的实施例包括至少部分地以硬件方式实现的逻辑，用于：动态地分配非易失性存储器的第一部分的逻辑; 响应于将设备进入待机状态的命令，将从易失性存储器的上下文数据的至少一部分存储到非易失性存储器的动态分配的第一部分的逻辑; 并且响应于所述装置的恢复操作，将所述上下文数据的至少一部分从所述非易失性存储器的第一部分复制到所述易失性存储器的逻辑，以及回收用于动态分配的所述非易失性存储器的所述第一部分。

26. 发明授权

US07971081B2 System and method for fast platform hibernate and resume 有权
标题翻译：用于快速平台休眠和恢复的系统和方法
公开(公告)号：US07971081B2
公开(公告)日：2011-06-28
申请号：US11965948
申请日：2007-12-28
申请人： Barnes Cooper , Faraz A. Siddiqi
发明人： Barnes Cooper , Faraz A. Siddiqi
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203
摘要： In some embodiments, an apparatus includes processor cores, a smaller non-volatile memory, a larger non-volatile memory to hold an operating system, programs, and data for use by the processor cores. The apparatus also includes volatile memory to act as system memory for the processor cores, and power management logic to control at least some aspects of power management. In response to a power state change command, a system context is stored in the smaller non-volatile memory followed by the volatile memory losing power, and in response to a resume command, the volatile memory receives power and receives at least a portion of the system context from the smaller non-volatile memory. Other embodiments are described.
摘要翻译：在一些实施例中，装置包括处理器核，更小的非易失性存储器，用于保存操作系统，程序和数据的更大的非易失性存储器以供处理器核心使用。该装置还包括作为用于处理器核的系统存储器的易失性存储器，以及功率管理逻辑以控制功率管理的至少一些方面。响应于电源状态改变命令，系统上下文存储在较小的非易失性存储器中，随后易失性存储器丢失电力，并且响应于恢复命令，易失性存储器接收电力并接收至少一部分系统上下文从较小的非易失性存储器。描述其他实施例。

27. 发明授权

US09032139B2 Memory allocation for fast platform hibernation and resumption of computing systems 有权
标题翻译：快速平台休眠和恢复计算系统的内存分配
公开(公告)号：US09032139B2
公开(公告)日：2015-05-12
申请号：US13730575
申请日：2012-12-28
申请人： Faraz A. Siddiqi , Francis R. Corrado , Barnes Cooper
发明人： Faraz A. Siddiqi , Francis R. Corrado , Barnes Cooper
IPC分类号： G06F12/02 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0246 , G06F12/0638 , G06F12/0871 , G06F2212/1028 , Y02D10/13
摘要： Memory allocation for fast platform hibernation and resumption of computing systems. An embodiment of an apparatus includes logic at least partially implemented in hardware, the logic to: dynamically allocate at least a first portion of a nonvolatile memory; in response to a command to enter the apparatus into a standby state, the logic to store at least a portion of a context data from a volatile memory to the dynamically allocated first portion of the nonvolatile memory; and in response to a resumption of operation of the apparatus, the logic to copy at least the portion of the context data from the first portion of the nonvolatile memory to the volatile memory, and to reclaim the first portion of the nonvolatile memory for dynamic allocation.
摘要翻译：快速平台休眠和恢复计算系统的内存分配。装置的实施例包括至少部分地以硬件方式实现的逻辑，用于：动态地分配非易失性存储器的第一部分的逻辑; 响应于将设备进入待机状态的命令，将从易失性存储器的上下文数据的至少一部分存储到非易失性存储器的动态分配的第一部分的逻辑; 并且响应于所述装置的恢复操作，将所述上下文数据的至少一部分从所述非易失性存储器的第一部分复制到所述易失性存储器的逻辑，以及回收用于动态分配的所述非易失性存储器的所述第一部分。

28. 发明申请

US20100125723A1 METHOD AND SYSTEM TO ENABLE FAST PLATFORM RESTART 有权
标题翻译：方法和系统启用快速平台重启
公开(公告)号：US20100125723A1
公开(公告)日：2010-05-20
申请号：US12274276
申请日：2008-11-19
申请人： Barnes Cooper , Faraz A. Siddiqi , Michael R. Rothman , Vincent J. Zimmer
发明人： Barnes Cooper , Faraz A. Siddiqi , Michael R. Rothman , Vincent J. Zimmer
IPC分类号： G06F9/24
CPC分类号： G06F9/4411
摘要： A method and system to perform a fast reset or restart of a platform by minimizing the hardware initialization of IO devices in the platform during a restart of the platform. The basic input/output system (BIOS) of the platform traps any software initiated reset request (SIRR) or warm reset. The BIOS restores the input/output (IO) devices coupled with the platform to their previous hardware state to avoid the full platform initialization when the SIRR is trapped. The restart of the platform can be performed in a fast manner as the full platform initialization is minimized.
摘要翻译：一种方法和系统，通过在平台的重新启动期间最小化平台中的IO设备的硬件初始化来执行平台的快速重置或重新启动。平台的基本输入/输出系统（BIOS）捕获任何软件启动的复位请求（SIRR）或热复位。 BIOS将与平台耦合的输入/输出（IO）设备恢复到其先前的硬件状态，以避免SIRR被捕获时的完整平台初始化。当平台初始化最小化时，平台的重新启动可以以快速的方式执行。

29. 发明授权

US07036005B2 Method and apparatus for modifying the contents of revision identification register 有权
公开(公告)号：US07036005B2
公开(公告)日：2006-04-25
申请号：US10039652
申请日：2001-12-31
申请人： Rajeev K. Nalawadi , Faraz A. Siddiqi
发明人： Rajeev K. Nalawadi , Faraz A. Siddiqi
IPC分类号： G06F12/14
CPC分类号： G06F9/4411
摘要： An embodiment for modifying the contents of a revision identification register includes a revision identification register that is both readable and writable (the contents of the revision identification register are modifiable). A revision identification modification bit is also included. The contents of the revision identification register are only modifiable when the revision identification modification bit is set to indicate that writes to the revision identification register will be accepted.

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