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    • 2. 发明授权
    • Fast platform hibernation and resumption of computing systems
    • 快速平台休眠和恢复计算系统
    • US09436251B2
    • 2016-09-06
    • US13996480
    • 2011-10-01
    • Barnes CooperFaraz A. Siddiqi
    • Barnes CooperFaraz A. Siddiqi
    • G06F1/00G06F1/32G06F9/44G06F21/81G06F3/06G06F12/02G06F13/00
    • G06F1/32G06F1/3203G06F1/3275G06F3/0608G06F9/4418G06F12/023G06F13/00G06F21/81G06F2212/2022G06F2212/205G06F2212/401Y02D10/44
    • Fast platform hibernation and resumption for computing systems. An embodiment of an apparatus includes a volatile system memory, a nonvolatile memory, and a processor to operate according to an operating system, the processor to transition the apparatus to a first reduced power state upon receipt of a request, the transition to the first reduced power state including the processor to store context information for the computer in the volatile system memory. The apparatus further includes logic to transition the apparatus to a second reduced power state, the logic to copy the context data from the volatile system memory to the nonvolatile memory for the transition to the second reduced power state, where copying of the context data includes the logic to scan the volatile system memory to locate non-active memory elements in the volatile system memory, eliminate the non-active memory elements from the volatile system memory to generate compressed context data, and store the compressed context data in the nonvolatile memory.
    • 快速平台休眠和恢复计算系统。 装置的实施例包括易失性系统存储器,非易失性存储器和根据操作系统操作的处理器,所述处理器在接收到请求时将装置转换到第一降低功率状态,转换到第一减少 电源状态包括处理器,用于存储易失性系统存储器中的计算机的上下文信息。 该装置还包括将装置转换到第二降低功率状态的逻辑,将上下文数据从易失性系统存储器复制到非易失性存储器以转换到第二降低功率状态的逻辑,其中上下文数据的复制包括 扫描易失性系统存储器以定位易失性系统存储器中的非活动存储器元件的逻辑,从易失性系统存储器中消除非活动存储器元件以产生压缩上下文数据,并将压缩上下文数据存储在非易失性存储器中。
    • 7. 发明申请
    • FAST PLATFORM HIBERNATION AND RESUMPTION OF COMPUTING SYSTEMS
    • 快速平台自动化和计算机系统恢复
    • US20130290760A1
    • 2013-10-31
    • US13996480
    • 2011-10-01
    • Barnes CooperFaraz A. Siddiqi
    • Barnes CooperFaraz A. Siddiqi
    • G06F1/32
    • G06F1/32G06F1/3203G06F1/3275G06F3/0608G06F9/4418G06F12/023G06F13/00G06F21/81G06F2212/2022G06F2212/205G06F2212/401Y02D10/44
    • Fast platform hibernation and resumption for computing systems. An embodiment of an apparatus includes a volatile system memory, a nonvolatile memory, and a processor to operate according to an operating system, the processor to transition the apparatus to a first reduced power state upon receipt of a request, the transition to the first reduced power state including the processor to store context information for the computer in the volatile system memory. The apparatus further includes logic to transition the apparatus to a second reduced power state, the logic to copy the context data from the volatile system memory to the nonvolatile memory for the transition to the second reduced power state, where copying of the context data includes the logic to scan the volatile system memory to locate non-active memory elements in the volatile system memory, eliminate the non-active memory elements from the volatile system memory to generate compressed context data, and store the compressed context data in the nonvolatile memory.
    • 快速平台休眠和恢复计算系统。 装置的实施例包括易失性系统存储器,非易失性存储器和根据操作系统操作的处理器,所述处理器在接收到请求时将装置转换到第一降低功率状态,转换到第一减少 电源状态包括处理器,用于存储易失性系统存储器中的计算机的上下文信息。 该装置还包括将装置转换到第二降低功率状态的逻辑,将上下文数据从易失性系统存储器复制到非易失性存储器以转换到第二降低功率状态的逻辑,其中上下文数据的复制包括 扫描易失性系统存储器以定位易失性系统存储器中的非活动存储器元件的逻辑,从易失性系统存储器中消除非活动存储器元件以产生压缩上下文数据,并将压缩上下文数据存储在非易失性存储器中。
    • 9. 发明申请
    • SYSTEM AND METHOD FOR FAST PLATFORM HIBERNATE AND RESUME
    • 快速平台自由和恢复的系统和方法
    • US20090172439A1
    • 2009-07-02
    • US11965948
    • 2007-12-28
    • Barnes CooperFaraz A. Siddiqi
    • Barnes CooperFaraz A. Siddiqi
    • G06F1/32
    • G06F1/3203
    • In some embodiments, an apparatus includes processor cores, a smaller non-volatile memory, a larger non-volatile memory to hold an operating system, programs, and data for use by the processor cores. The apparatus also includes volatile memory to act as system memory for the processor cores, and power management logic to control at least some aspects of power management. In response to a power state change command, a system context is stored in the smaller non-volatile memory followed by the volatile memory losing power, and in response to a resume command, the volatile memory receives power and receives at least a portion of the system context from the smaller non-volatile memory. Other embodiments are described.
    • 在一些实施例中,装置包括处理器核,更小的非易失性存储器,用于保存操作系统,程序和数据的更大的非易失性存储器以供处理器核心使用。 该装置还包括作为用于处理器核的系统存储器的易失性存储器,以及功率管理逻辑以控制功率管理的至少一些方面。 响应于电源状态改变命令,系统上下文存储在较小的非易失性存储器中,随后易失性存储器丢失电力,并且响应于恢复命令,易失性存储器接收电力并接收至少一部分 系统上下文从较小的非易失性存储器。 描述其他实施例。