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21. 发明专利

JP2010165896A Semiconductor device and method for manufacturing therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010165896A
公开(公告)日：2010-07-29
申请号：JP2009007397
申请日：2009-01-16
申请人： Nec Corp , 日本電気株式会社
发明人： OKAMOTO YASUHIRO , ANDO YUJI , NAKAYAMA TATSUO , OTA KAZUKI , INOUE TAKASHI , MIYAMOTO HIRONOBU , ENDO KAZUTOMI
IPC分类号： H01L21/338 , H01L21/28 , H01L29/417 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which possesses reverse blocking characteristics and achieves a normally-off characteristic, on-state resistance, and the suppression of off-state current.
SOLUTION: The semiconductor device includes a semiconductor laminate structure 10 containing a channel layer 14 and an electron supply layer 15, a source electrode 1 and a drain electrode 4 formed spaced apart on the semiconductor laminate structure 10, an insulating film 22 formed between the source electrode 1 and the drain electrode 4, and a gate electrode 2 formed on the insulating film, wherein a reverse current between the drain electrode 4 and the semiconductor laminate structure 10 is blocked.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供具有反向阻挡特性并实现常态特性，导通状态电阻和截止电流的抑制的半导体器件。解决方案：半导体器件包括半导体层叠结构10，其包含在半导体层叠结构10上间隔开形成的沟道层14和电子供给层15，源电极1和漏电极4，形成绝缘膜22 在源极电极1和漏极电极4之间以及形成在绝缘膜上的栅极电极2，其中漏极电极4和半导体叠层结构体10之间的反向电流被阻挡。版权所有（C）2010，JPO＆INPIT

22. 发明专利

JP2009021458A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009021458A
公开(公告)日：2009-01-29
申请号：JP2007183853
申请日：2007-07-13
申请人： Nec Corp , 日本電気株式会社
发明人： NAKAYAMA TATSUO , MIYAMOTO HIRONOBU , ANDO YUJI , OKAMOTO YASUHIRO , INOUE TAKASHI , OTA KAZUKI , WAKEJIMA AKIO , MURASE YASUHIRO , KURODA NAOTAKA , TANOMURA MASAHIRO
IPC分类号： H01L21/338 , H01L21/28 , H01L29/417 , H01L29/423 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of discharging holes generated by collision ionization to the outside while keeping excellent transistor characteristics. SOLUTION: The semiconductor device includes a substrate 100, a group III nitride semiconductor multilayer film provided on the substrate 100, and a gate electrode 112, a source electrode 110 and a drain electrode 114 provided on the upper part of the group III nitride semiconductor multilayer film. The group III nitride semiconductor multilayer film includes a hole transit layer 104, an electron transit layer 106 and an electron supply layer 108, and the hole transit layer 104 and the gate electrode 112 are electrically connected by a conductor. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其能够在保持优异的晶体管特性的同时将通过碰撞电离产生的空穴放电到外部。解决方案：半导体器件包括衬底100，设置在衬底100上的III族氮化物半导体多层膜，以及设置在III族上部的栅电极112，源电极110和漏电极114 氮化物半导体多层膜。 III族氮化物半导体多层膜包括空穴传输层104，电子传输层106和电子供给层108，并且空穴传输层104和栅电极112通过导体电连接。版权所有（C）2009，JPO＆INPIT

23. 发明专利

JP2008218696A Field-effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：JP2008218696A
公开(公告)日：2008-09-18
申请号：JP2007053889
申请日：2007-03-05
申请人： Nec Corp , 日本電気株式会社
发明人： MIYAMOTO HIRONOBU , ANDO YUJI , INOUE TAKASHI , NAKAYAMA TATSUO , OKAMOTO YASUHIRO , WAKEJIMA AKIO , OTA KAZUKI , MURASE YASUHIRO , YAMANOGUCHI KATSUMI
IPC分类号： H01L21/338 , H01L21/318 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a high output nitride semiconductor transistor having a low current collapse and a low gate leakage current.
SOLUTION: In the transistor comprises a buffer layer 2, a GaN channel layer 3, and an AlGaN electron supply layer 4 formed on a substrate 1. A source electrode 5, a drain electrode 6 and a gate electrode 7 are formed on the surface of the AlGaN electron supply layer 4, the surface of the exposed AlGaN electron supply layer 4 is covered with a fluorine-containing insulating film 8 containing a fluorine, such as a fluorine-containing SiN film.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供具有低电流塌陷和低栅极泄漏电流的高输出氮化物半导体晶体管。解决方案：晶体管包括形成在基板1上的缓冲层2，GaN沟道层3和AlGaN电子供给层4.源电极5，漏电极6和栅电极7形成在 AlGaN电子供给层4的表面，露出的AlGaN电子供给层4的表面被含氟的氟系绝缘膜8覆盖，例如含氟SiN膜。版权所有（C）2008，JPO＆INPIT

24. 发明公开

EP1978550A4 FIELD EFFECT TRANSISTOR, AND MULTILAYERED EPITAXIAL FILM FOR USE IN PREPARATION OF FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：场效应晶体管和多层外延用在场效应晶体管的制备
公开(公告)号：EP1978550A4
公开(公告)日：2009-07-22
申请号：EP06822252
申请日：2006-10-25
申请人： NEC CORP
发明人： INOUE TAKASHI , NAKAYAMA TATSUO , ANDO YUJI , MURASE YASUHIRO , OTA KAZUKI , MIYAMOTO HIRONOBU , YAMANOGUCHI KATSUMI , KURODA NAOTAKA , WAKEJIMA AKIO , OKAMOTO YASUHIRO
IPC分类号： H01L21/338 , H01L29/778 , H01L29/812
CPC分类号： H01L29/7783 , H01L29/0607 , H01L29/155 , H01L29/2003 , H01L29/205 , H01L29/42316 , H01L29/7787
摘要： In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a ‰¥ 5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 A) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

25. 发明公开

EP2003686A4 FIELD EFFECT TRANSISTOR 有权转让
标题翻译：场效应晶体管
公开(公告)号：EP2003686A4
公开(公告)日：2009-08-19
申请号：EP07736989
申请日：2007-03-29
申请人： NEC CORP
发明人： ANDO YUJI , MIYAMOTO HIRONOBU , NAKAYAMA TATSUO , OKAMOTO YASUHIRO , INOUE TAKASHI , MURASE YASUHIRO , OTA KAZUKI , WAKEJIMA AKIO , KURODA NAOTAKA
IPC分类号： H01L21/338 , H01L21/28 , H01L29/417 , H01L29/778 , H01L29/812
CPC分类号： H01L29/7787 , H01L29/2003

26. 发明公开

EP1901341A4 FIELD EFFECT TRANSISTOR 审中-公开
公开(公告)号：EP1901341A4
公开(公告)日：2009-07-15
申请号：EP06766607
申请日：2006-06-12
申请人： NEC CORP
发明人： MIYAMOTO HIRONOBU , ANDO YUJI , OKAMOTO YASUHIRO , NAKAYAMA TATSUO , INOUE TAKASHI , OTA KAZUKI , WAKEJIMA AKIO , KASAHARA KENSUKE , MURASE YASUHIRO , MATSUNAGA KOHJI , YAMANOGUCHI KATSUMI , SHIMAWAKI HIDENORI
IPC分类号： H01L21/338 , H01L29/06 , H01L29/40 , H01L29/778 , H01L29/812
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/402 , H01L29/404 , H01L29/802 , H01L29/812

27. 发明公开

EP1901342A4 FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：场效应晶体管
公开(公告)号：EP1901342A4
公开(公告)日：2009-07-22
申请号：EP06766608
申请日：2006-06-12
申请人： NEC CORP
发明人： MIYAMOTO HIRONOBU , ANDO YUJI , OKAMOTO YASUHIRO , NAKAYAMA TATSUO , INOUE TAKASHI , OTA KAZUKI , WAKEJIMA AKIO , KASAHARA KENSUKE , MURASE YASUHIRO , MATSUNAGA KOHJI , YAMANOGUCHI KATSUMI , SHIMAWAKI HIDENORI
IPC分类号： H01L21/338 , H01L29/778 , H01L29/812
CPC分类号： H01L29/404 , H01L29/7783 , H01L29/7787 , H01L29/802 , H01L29/812

28. 发明公开

EP1962338A4 FIELD EFFECT TRANSISTOR 审中-公开
标题翻译： FELDEFFEKTTRANSISTOR
公开(公告)号：EP1962338A4
公开(公告)日：2009-07-15
申请号：EP06834508
申请日：2006-12-12
申请人： NEC CORP
发明人： MATSUNAGA KOUJI , OTA KAZUKI , OKAMOTO YASUHIRO , NAKAYAMA TATSUO , WAKEJIMA AKIO , ANDO YUJI , MIYAMOTO HIRONOBU , INOUE TAKASHI , MURASE YASUHIRO
IPC分类号： H01L21/338 , H01L21/335 , H01L29/06 , H01L29/778 , H01L29/812
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/66462
摘要： A semiconductor device (100) is provided with an undoped GaN electron transport layer (105); an AlGaN electron supply layer (106) arranged in contact with the undoped GaN electron transport layer (105); an undoped GaN layer (107) arranged on the AlGaN electron supply layer (106); a source electrode (101) and a drain electrode (103) arranged on the undoped GaN layer (107), being separated from one another; a recessed section (111), which is arranged in a region between the source electrode (101) and the drain electrode (103) and penetrating the undoped GaN layer (107); a gate electrode (102) which is embedded in the recessed section (111) and being brought into contact with the AlGaN electron supply layer (106) at the bottom plane; and a SiN film (108) arranged on the undoped GaN layer (107) in the region between the gate electrode (102) and the drain electrode (103).
摘要翻译：半导体器件（100）设置有未掺杂的GaN电子传输层（105）; 与未掺杂的GaN电子传输层（105）接触布置的AlGaN电子供应层（106）; 布置在所述AlGaN电子供给层（106）上的未掺杂的GaN层（107）; 布置在未掺杂的GaN层（107）上的源电极（101）和漏电极（103），彼此分离; 设置在所述源电极与所述漏电极之间的区域并贯穿所述未掺杂的GaN层的凹部; 嵌入凹部（111）内并在底面与AlGaN电子供给层（106）接触的栅电极（102）以及在栅电极（102）和漏电极（103）之间的区域中布置在未掺杂的GaN层（107）上的SiN膜（108）。

29. 发明专利

JP2001085334A MANUFACTURE OF III-V COMPOUND SEMICONDUCTOR CRYSTAL LAMINATE 失效
公开(公告)号：JP2001085334A
公开(公告)日：2001-03-30
申请号：JP26357299
申请日：1999-09-17
申请人： NEC CORP
发明人： OTA KAZUKI , MIYAMOTO HIRONOBU
IPC分类号： H01L21/205
摘要： PROBLEM TO BE SOLVED: To enable a hetero-junction interface very steep at an atomic layer level to be formed without forming a modified layer which contains As and P, by a method wherein a substrate temperature is specified, only carrier gas is supplied after IV material gas is fed, and second V material gas and tertiary butyl second material gas are supplied. SOLUTION: When an undoped InGaAs channel layer, an N-type InGaP electron supply layer, and an N-type AlGaAs Schottky layer are successively grown, carrier gas, III material gas, and IV material gas of AsH3 or PH3 fed to grow a first semiconductor crystal layer that forms the lower part of a hetero-junction interface, a substrate temperature is kept at a temperature of 450 to 650 deg.C, only III material gas is stopped form being fed, and then IV material gas is stopped from being supplied. After a prescribed time elapses, carrier gas, a second V material gas of AsH3 or PH3, and tertiary butyl second V material gas are supplied for a prescribed time, and then carrier gas, III material gas, and second V material gas are supplied.

30. 发明专利

JP2006222160A FIELD EFFECT TRANSISTOR AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2006222160A
公开(公告)日：2006-08-24
申请号：JP2005032217
申请日：2005-02-08
申请人： NEC CORP
发明人： OTA KAZUKI
IPC分类号： H01L29/812 , H01L21/28 , H01L21/338 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/778 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a field effect transistor which reduces a parasitic resistance and to improve the performance and reliability of an element. SOLUTION: The field effect transistor includes a laminate having a channel layer 13 consisting of a nitride semiconductor on a substrate, and an electron supply layer 14 which is located on the channel layer 13 and consisting of the nitride semiconductor. Further, the transistor comprises a source electrode 16, a drain electrode 17, and a gate electrode 18 provided on this laminate front surface. In the channel layer 13, n-type impurity concentrations under the source electrode 16 and the drain electrode 17 are higher than the n-type impurity concentration under the gate electrode 18. The field effect transistor in which, in the electron supply layer 14, the n-type impurity concentrations under the source electrode 16 and the drain electrode 17 are higher than the n-type impurity concentration under the gate electrode 18, is provided. COPYRIGHT: (C)2006,JPO&NCIPI

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