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1. 发明公开

EP1901341A4 FIELD EFFECT TRANSISTOR 审中-公开
公开(公告)号：EP1901341A4
公开(公告)日：2009-07-15
申请号：EP06766607
申请日：2006-06-12
申请人： NEC CORP
发明人： MIYAMOTO HIRONOBU , ANDO YUJI , OKAMOTO YASUHIRO , NAKAYAMA TATSUO , INOUE TAKASHI , OTA KAZUKI , WAKEJIMA AKIO , KASAHARA KENSUKE , MURASE YASUHIRO , MATSUNAGA KOHJI , YAMANOGUCHI KATSUMI , SHIMAWAKI HIDENORI
IPC分类号： H01L21/338 , H01L29/06 , H01L29/40 , H01L29/778 , H01L29/812
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/402 , H01L29/404 , H01L29/802 , H01L29/812

2. 发明公开

EP1901342A4 FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：场效应晶体管
公开(公告)号：EP1901342A4
公开(公告)日：2009-07-22
申请号：EP06766608
申请日：2006-06-12
申请人： NEC CORP
发明人： MIYAMOTO HIRONOBU , ANDO YUJI , OKAMOTO YASUHIRO , NAKAYAMA TATSUO , INOUE TAKASHI , OTA KAZUKI , WAKEJIMA AKIO , KASAHARA KENSUKE , MURASE YASUHIRO , MATSUNAGA KOHJI , YAMANOGUCHI KATSUMI , SHIMAWAKI HIDENORI
IPC分类号： H01L21/338 , H01L29/778 , H01L29/812
CPC分类号： H01L29/404 , H01L29/7783 , H01L29/7787 , H01L29/802 , H01L29/812

3. 发明专利

JP2002261271A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
公开(公告)号：JP2002261271A
公开(公告)日：2002-09-13
申请号：JP2001057408
申请日：2001-03-01
申请人： NEC CORP
发明人： AZUMA KOJI , MIYOSHI YOSUKE , HARIMA FUMIO , TANOMURA MASAHIRO , SHIMAWAKI HIDENORI
IPC分类号： H01L21/331 , H01L29/737
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same with which collector resistance is reduced and reliability is improved. SOLUTION: This semiconductor device includes a first conductive type array layer (4), having an ordered array structure which is formed on a first conductivity-type collector contact layer (3) connected to a collector electrode (13), a first conductivity-type compensated layer (5) formed on the array layer (4), a first conductivity-type collector layer (6) formed on the compensated layer (5), a base layer (7) formed on the collector layer (6) and connected to a base electrode (9), and emitter layers (8, 10 and 11) formed on the base layer (7) and connected to an emitter electrode (12).

4. 发明专利

JPH03240269A BIPOLAR TRANSISTOR AND ITS MANUFACTURE 失效
公开(公告)号：JPH03240269A
公开(公告)日：1991-10-25
申请号：JP3610090
申请日：1990-02-19
申请人： NEC CORP
发明人： SHIMAWAKI HIDENORI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737
摘要： PURPOSE:To manufacture a bipolar transistor of compound semiconductor excellent in operation speed and high frequency characteristics, by providing an emitter base junction part with an AlbGa1-bAs layer (a in a specified portion. An AuGeNi layer 6 is vapor-deposited on the layer 5; by using a photoresist film 11 as a mask, an SiO2 film 9 and the film 11 are formed; the film 9 and the layer 6 are eliminated. The surface of the layer 4 is exposed by etching the layer 5; a photoresist mask 12 is formed on the region 10; an AuZnNi layer 7 is vapor-deposited. The film 12 is eliminated; a photoresist film 13 with a specified pattern is formed; the layer 7 is eliminated by using the film 13 as a mask. An AuGeNi layer 8 is vapor-deposited by using the film 13 as a mask; the film 13 is dissolved in organic solvent, thereby forming desired semiconductor.

5. 发明专利

JPH02303068A SEMICONDUCTOR LAMINATION STRUCTURE AND SEMICONDUCTOR ELEMENT HAVING SAME 失效
公开(公告)号：JPH02303068A
公开(公告)日：1990-12-17
申请号：JP12500389
申请日：1989-05-17
申请人： NEC CORP
发明人： SHIMAWAKI HIDENORI
IPC分类号： H01L29/73 , H01L21/20 , H01L21/331 , H01L21/338 , H01L29/201 , H01L29/737 , H01L29/812 , H01L33/06 , H01L33/12 , H01L33/30 , H01L33/40 , H01S5/00
摘要： PURPOSE:To obtain a graded junction type heterojunction whose composition controllability and composition uniformity are improved by controlling the ratio of layer numbers of first semiconductor layers and second semiconductor layers, and changing a graded layer. CONSTITUTION:On a semi-insulative substrate 3 composed of Fe-doped InP, an undoped I-InP layer 4 and a graded layer are formed in order, and a buffer layer is formed. On the buffer layer, an S-doped N-In0.53Ga0.47As layer 11 is formed. This graded layer is formed by periodically laminating the undoped I-InP layers and the undoped I-In0.53Ga0.47As layers 11. By controlling the ratio of the number of the layers, the composition is changed. As to the N-In0.53Ga0.47 As layer 11 obtained in this manner, misfit dislocation is reduced, and surface state is excellent.

6. 发明专利

JPH05251404A 失效
公开(公告)号：JPH05251404A
公开(公告)日：1993-09-28
申请号：JP4646392
申请日：1992-03-04
申请人： NEC CORP
发明人： AMAMIYA YASUSHI , SHIMAWAKI HIDENORI
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065
摘要： PURPOSE:To provide a method for dry etching a dielectric layer formed on a semiconductor layer without causing damage onto the underlying semiconductor layer. CONSTITUTION:An Al layer 6 is interposed between a GaAs semiconductor layer 1 and a dielectric layer 3. Consequently, the semiconductor layer 1 is protected against damage when the dielectric layer 3 is subjected to reactive ion etching with CF4.

7. 发明专利

JPH0376217A METHOD OF FORMATION FOR INDIUM ARSENIDE LAYER 失效
公开(公告)号：JPH0376217A
公开(公告)日：1991-04-02
申请号：JP21229389
申请日：1989-08-18
申请人： NEC CORP
发明人： SHIMAWAKI HIDENORI , KATOU YOSHITAKE
IPC分类号： H01L21/205
摘要： PURPOSE:To alleviate the substrate temperature dependency of growth speed and to contrive improvement in film thickness controllability by a method wherein a first raw gas, containing a group III element, contains an In chloride, a second raw gas, containing a group V element, contains As, and the (111) B face is used as the crystal face orientation of the substrate. CONSTITUTION:A (111) B face (group V element stabilized face) is used as the crystal face orientation of a substrate, and the growth of a mono-molecular layer is made possible by using an In chloride for raw gas. The In chloride, generated by the reaction of an In source and an HC1, and the As compound, generated by the thermal decomposition of AsH, are used for raw gas, the temperature of In source is set at 650 deg.C, the partial pressure of the HC1 to be fed to the In source and AsH3 feeding partial pressure are set at 7.5X10 atm and 1.4X10 atm. By using the (111) B substrate, the growth of film thick ness per cycle is made uniform in the temperature region of 375 deg.C or lower irrespective of substrate temperature. When an InAs layer is formed, the region where growth speed becomes constant irrespective of substrate temperature is expanded, and stabilized InAs can be grown for almost every molecular layer in the above-mentioned temperature region.

8. 发明专利

JPH02271669A SEMICONDUCTOR LAMINATED STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING SAME 失效
公开(公告)号：JPH02271669A
公开(公告)日：1990-11-06
申请号：JP9455589
申请日：1989-04-13
申请人： NEC CORP
发明人： SHIMAWAKI HIDENORI
IPC分类号： C30B23/08 , C30B29/40 , H01L21/20 , H01L21/203 , H01L29/201
摘要： PURPOSE:To form a graded junction type hetero junction type hetero junction by forming a graded layer into a periodic laminate structure of two or more kinds of a binary compound semiconductor layers each of which takes as ingredients constituent elements of a semiconductor layer A and a semiconductor layer B, and altering the period of the periodic laminate structure. CONSTITUTION:For an InAs layer 2 and a GaAs layer 3, lattice matching with InP is taken into consideration, and the ratio of the layer number therebetween is kept at a predetermined one (1:1) such that they exhibit an equivalent crystal layer to In0.5As. More specifically, the layer number ratio in the In0.5Ga0.5As layer in which the InP layer, the InAs layer, and the GaAs layer are laminated, is progressively altered, whereby there is formed a graded layer in which the composition is changed from the InP to In0.5Ga0.5As. Further, a tetra mixed crystal semiconductor layer can be formed, which has a composition corresponding to In0.6Ga0.4As0.8P0.2, by alternately laminating three InP layers, one InAs layer, and one GaAs layer and by alternately laminating In0.8Ga0.2As0.6P0.6, or InP layer, two InAs layers, and two GaAs layer. Hereby, a graded junction type hetero junction improved in composition uniformity is yielded.

9. 发明专利

JPH0278226A HETEROJUNCTION BIPOLAR TRANSISTOR AND ITS MANUFACTURE 失效
公开(公告)号：JPH0278226A
公开(公告)日：1990-03-19
申请号：JP23034288
申请日：1988-09-13
申请人： NEC CORP
发明人： TANAKA SHINICHI , SHIMAWAKI HIDENORI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737
摘要： PURPOSE:To form a fine structure of high reliability by a method wherein a difference in height between an upper end face of an outer base layer in an external transistor region and a base-emitter junction face inside an intrinsic transistor region is made smaller than a thickness of an intrinsic base layer. CONSTITUTION:A collector contact layer (n GaAs) 2 and a collector layer (n GaAs) 3 are formed one after another on a semiinsulating substrate 1. Then, a protective film 81 composed of SiO2 is formed in a prescribed region; the layer 3 is etched by making use of the protective film as a mask; a high- resistance layer (mi-GaAs Iayer) 3i is filled in such a way that a semiconductor crystal plane of an outer base layer (p GaAs) 4c is nearly flat. Then, a protective film 82 composed of an SiO2 film is grown on the whole surface; the film is coated with a photoresist as a protective film 9; this film is flattened; the film 9 is etched; the exposed films 82, 81 are etched; the remaining film 9 is removed; a base layer 4 (p-GaAs), an emitter layer 5 (n-Al0.3Ga0.7As) and a contact layer (n GaAS) are grown again.

10. 发明专利

JPH01204411A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01204411A
公开(公告)日：1989-08-17
申请号：JP2947288
申请日：1988-02-09
申请人： NEC CORP
发明人： SHIMAWAKI HIDENORI
IPC分类号： C30B25/02 , H01L21/20 , H01L21/205 , H01L21/331 , H01L21/337 , H01L21/338 , H01L29/423 , H01L29/73 , H01L29/737 , H01L29/78 , H01L29/812
摘要： PURPOSE:To miniaturize the size of an element and to improve the high speed and high frequency characteristics of the element, by using a single element semiconductor as a mask, introducing selective growth, selectively forming a compound semiconductor layer, and epitaxially growing a high quality single crystal semiconductor layer on the mask. CONSTITUTION:A semiconductor layer 2 comprising undoped Ge on a semi- insulating substrate 1 comprising GaAs. Thereafter a photoresist film having a specified pattern for forming an opening part is formed on the semiconductor layer 2. With the photoresist film as a mask, the semiconductor layer 2 is removed by reactive ion beam etching, and the surface of the semi-insulating substrate 1 is exposed. Then, the photoresist film is removed. Thereafter, with the semiconductor layer 2 as a mask, a semiconductor layer 3 comprising p- GaAs is selectively formed on the semi-insulating substrate 1 at the opening part. A semiconductor layer 4 comprising N-AlGaAs is epitaxially grown and formed on the semiconductor layer 2 and the semiconductor layer 3. Thus, the element is miniaturized, and the high-speed and high-frequency characteristics can be improved.

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