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21. 发明申请

US20080151677A1 Memory device, memory controller and memory system 有权
标题翻译：内存设备，内存控制器和内存系统
公开(公告)号：US20080151677A1
公开(公告)日：2008-06-26
申请号：US11698286
申请日：2007-01-26
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C8/12
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
摘要翻译：提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中，在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。

22. 发明授权

US06515585B2 Reminder system 有权
标题翻译：提醒系统
公开(公告)号：US06515585B2
公开(公告)日：2003-02-04
申请号：US09748252
申请日：2000-12-27
申请人： Yoshinobu Yamamoto
发明人： Yoshinobu Yamamoto
IPC分类号： G08B700
CPC分类号： G08B3/1083
摘要： A reminder system operating at a specified location is provided. When an information ID (such as an “address C, B, AA, and bookstore”) transmitted from a small antenna station agrees with information (such as an “address C, B, AA, and bookstore”) stored in a memory of a reminder passing by the installation location of the small antenna station, the reminder outputs an alarm, and displays free messages (“The address here is C, B, AA” and “There is a bookstore”) on the display of the reminder. Thus, a user carrying the reminder is alerted to the business input in advance to the reminder.
摘要翻译：提供在指定位置操作的提醒系统。当从小型天线站发送的信息ID（诸如“地址C，B，AA和书店”）与存储在存储器中的信息（例如“地址C，B，AA和书店”）一致时通过小型天线站的安装位置的提示，提醒输出报警，并在提醒的显示上显示免费消息（“地址在这里是C，B，AA”和“有书店”）。因此，携带提醒的用户预先向业务输入提醒。

23. 发明授权

US06410574B1 Fungicidal composition and method for using the same 有权
公开(公告)号：US06410574B1
公开(公告)日：2002-06-25
申请号：US09362087
申请日：1999-07-28
申请人： Tsutomu Nishiguchi , Tsuyoshi Takemoto , Sohkichi Tajima , Yoshinobu Yamamoto
发明人： Tsutomu Nishiguchi , Tsuyoshi Takemoto , Sohkichi Tajima , Yoshinobu Yamamoto
IPC分类号： A01N43828
摘要： The present invention relates to a fungicidal composition obtained by mixing a 1,2,3-thiadiazole derivative of general formula (I) useful as a plant disease controller with at least one fungicide selected from the compounds having a fungicidal activity against plant diseases, and to a method for using the same: wherein R1 is hydrogen, alkyl or cycloalkyl and R2 is CO—Y—R3, wherein Y is O, S, NR4 or the like and R3 is hydrogen, alkyl, phenyl, 5- or 6-membered heterocycle or the like.

24. 发明授权

US5838770A Portable telephone system 失效
公开(公告)号：US5838770A
公开(公告)日：1998-11-17
申请号：US689359
申请日：1996-08-08
申请人： Yutaka Fukushima , Tetsuo Takemura , Shinichi Iwaki , Mitsuyoshi Hashida , Masao Wanami , Isao Shimbo , Mitsuhiro Wada , Hirofumi Udaki , Yoshihiro Kondo , Yoshinobu Yamamoto , Arata Nakagoshi , Kouichi Ohta , Hiroshi Kuwahara , Yumiko Watanabe
发明人： Yutaka Fukushima , Tetsuo Takemura , Shinichi Iwaki , Mitsuyoshi Hashida , Masao Wanami , Isao Shimbo , Mitsuhiro Wada , Hirofumi Udaki , Yoshihiro Kondo , Yoshinobu Yamamoto , Arata Nakagoshi , Kouichi Ohta , Hiroshi Kuwahara , Yumiko Watanabe
IPC分类号： H04B10/00 , H04B10/032 , H04B10/035 , H04B10/07 , H04B10/272 , H04B10/29 , H04M3/22 , H04W4/16 , H04W24/04 , H04W24/06 , H04W56/00 , H04W60/04 , H04W64/00 , H04W84/04 , H04W88/08 , H04W92/00 , H04M1/60
CPC分类号： H04W24/04 , H04B10/25754 , H04W84/042 , H04W24/06 , H04W4/16 , H04W60/04 , H04W64/006 , H04W88/08
摘要： Duplicate optical fibers connect between a base station controller and a radio base station for each route. The duplicate optical fiber is connected to each of the radio base stations for each route through a star coupler. The radio base stations are arranged in each of areas so that the radio base stations for different routes are arranged adjacent to each other.

25. 发明授权

US5353281A Intermittenceless switching system 失效
标题翻译：无间歇切换系统
公开(公告)号：US5353281A
公开(公告)日：1994-10-04
申请号：US889952
申请日：1992-05-29
申请人： Hiroshi Kuwahara , Kazuhiro Suzuki , Toshikazu Sasa , Kenzo Urabe , Arata Nakagoshi , Hideya Suzuki , Yohichi Ogawa , Tsuneo Furuya , Yoshinobu Yamamoto
发明人： Hiroshi Kuwahara , Kazuhiro Suzuki , Toshikazu Sasa , Kenzo Urabe , Arata Nakagoshi , Hideya Suzuki , Yohichi Ogawa , Tsuneo Furuya , Yoshinobu Yamamoto
IPC分类号： H04Q7/22 , H04Q7/28 , H04Q11/04
CPC分类号： H04Q11/04
摘要： An intermittenceless switching system includes two speech path memories having sufficient capacity to store a single frame of data having a plurality of time slots. The incoming data is stored in one memory, while the outgoing data is read from the other memory. A control circuit continuously alternates the read/write functions between the two memories. A control memory is used to store switch control information. The system includes a buffer memory that is present between a data processor and the control memory to prevent switch operation during data transmission. The system also includes a monitoring circuit for detecting an indication bit signifying the presence or absence of data in the time slot.
摘要翻译：无间歇切换系统包括具有足够的容量来存储具有多个时隙的单个数据帧的两个语音路径存储器。输入数据存储在一个存储器中，而从其他存储器读取输出数据。控制电路在两个存储器之间连续交替读/写功能。控制存储器用于存储开关控制信息。该系统包括存在于数据处理器和控制存储器之间的缓冲存储器，以防止在数据传输期间的开关操作。该系统还包括用于检测表示时隙中是否存在数据的指示位的监视电路。

26. 发明授权

US08469751B2 Electrical connector and harness 有权
标题翻译：电连接器和线束
公开(公告)号：US08469751B2
公开(公告)日：2013-06-25
申请号：US13424554
申请日：2012-03-20
申请人： Nobuyasu Oiri , Masakazu Kuroiwa , Yusuke Obata , Yoshinobu Yamamoto
发明人： Nobuyasu Oiri , Masakazu Kuroiwa , Yusuke Obata , Yoshinobu Yamamoto
IPC分类号： H01R13/502
CPC分类号： H01R13/4223 , H01R43/22
摘要： A waterproof connector includes a female contact, a housing, and a retainer. The housing includes a first inner wall surface, a second inner wall surface, a first engaging part, and a lance. The female contact includes a pressed surface that is pressed by the lance, and a first engaged part that is formed to protrude in a direction away from the pressed surface. A second engaging part is formed in the housing and a second engaged part that can be engaged with the second engaging part is formed in the female contact so that a second engagement between the housing and the female contact is achieved on a side opposite to the side of a first engagement between the first engaging part and the first engaged part with respect to a central axis of the female contact.
摘要翻译：防水连接器包括阴接触件，壳体和保持器。壳体包括第一内壁表面，第二内壁表面，第一接合部分和喷枪。阴接触件包括被喷枪按压的压制表面和形成为沿远离压制表面的方向突出的第一接合部分。第二接合部分形成在壳体中，并且可以与第二接合部分接合的第二接合部分形成在阴接触件中，使得在与侧面相对的一侧上实现壳体和阴接触件之间的第二接合第一接合部分和第一接合部分之间相对于阴接触件的中心轴线的第一接合。

27. 发明授权

US08077537B2 Memory device, memory controller and memory system 有权
标题翻译：内存设备，内存控制器和内存系统
公开(公告)号：US08077537B2
公开(公告)日：2011-12-13
申请号：US12612215
申请日：2009-11-04
申请人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1027 , G11C8/12 , G11C11/40618 , G11C11/4087
摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.
摘要翻译：提供了一种存储装置，其中已经解决了由存储装置的刷新操作引起的有效带宽的减少，存储装置的存储器控制器及其存储器系统。响应于来自存储器控制器的命令操作的存储器件具有分别具有存储器核心的多个存储体，包括存储器单元阵列和解码器，并且由存储体地址选择; 以及控制电路，其响应于后台刷新命令使由所述存储器控制器设置的刷新对象组内的存储器核心依次执行对应于由所述存储器控制器设置的刷新突发长度的次数的刷新操作，并且响应于正常操作命令，在由存储器核心执行的刷新操作期间进一步使存储器内的存储器核心在刷新对象组之外并由存储体地址选择以执行与正常操作命令相对应的正常存储器操作在刷新目标银行。

28. 发明授权

US08004921B2 Memory device, memory controller and memory system 有权
公开(公告)号：US08004921B2
公开(公告)日：2011-08-23
申请号：US12612247
申请日：2009-11-04
申请人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1027 , G11C8/12 , G11C11/40618 , G11C11/4087
摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

29. 发明授权

US07814294B2 Memory device, memory controller and memory system 有权
标题翻译：内存设备，内存控制器和内存系统
公开(公告)号：US07814294B2
公开(公告)日：2010-10-12
申请号：US11698286
申请日：2007-01-26
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G06F12/06
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
摘要翻译：提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中，在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。

30. 发明申请

US20100172200A1 MEMORY DEVICE, MEMORY CONTROLLER AND MEMORY SYSTEM 有权
标题翻译：存储器件，存储器控制器和存储器系统
公开(公告)号：US20100172200A1
公开(公告)日：2010-07-08
申请号：US12612247
申请日：2009-11-04
申请人： Tomohiro KAWAKUBO , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Tomohiro KAWAKUBO , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/406 , G11C7/1027 , G11C8/12 , G11C11/40618 , G11C11/4087
摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.
摘要翻译：提供了一种存储装置，其中已经解决了由存储装置的刷新操作引起的有效带宽的减少，存储装置的存储器控制器及其存储器系统。响应于来自存储器控制器的命令操作的存储器件具有分别具有存储器核心的多个存储体，包括存储器单元阵列和解码器，并且由存储体地址选择; 以及控制电路，其响应于后台刷新命令使由所述存储器控制器设置的刷新对象组内的存储器核心依次执行对应于由所述存储器控制器设置的刷新突发长度的次数的刷新操作，并且响应于正常操作命令，在由存储器核心执行的刷新操作期间进一步使存储器内的存储器核心在刷新对象组之外并由存储体地址选择以执行与正常操作命令相对应的正常存储器操作在刷新目标银行。

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