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21. 发明授权

US3993981A Apparatus for processing data transfer requests in a data processing system 失效
标题翻译：用于在数据处理系统中处理数据传送请求的装置
公开(公告)号：US3993981A
公开(公告)日：1976-11-23
申请号：US591964
申请日：1975-06-30
申请人： Frank V. Cassarino, Jr. , George J. Barlow , George J. Bekampis , John W. Conway , Richard A. Lemay , David B. O'Keefe , Douglas L. Riikonen , William E. Woods
发明人： Frank V. Cassarino, Jr. , George J. Barlow , George J. Bekampis , John W. Conway , Richard A. Lemay , David B. O'Keefe , Douglas L. Riikonen , William E. Woods
IPC分类号： G06F9/46 , G06F13/18 , G06F13/37 , G06F13/378 , G06F13/42 , G06F3/04 , G06F13/00
CPC分类号： G06F13/378 , G06F13/18 , G06F13/4213
摘要： In a data processing system having a plurality of units coupled for the transfer of information therebetween over a common electrical bus during asynchronously generated information bus transfer cycles, the units are coupled in a priority network and depending upon their respective priority may gain access to the bus before a lower priority unit is so enabled. Each one of the units includes apparatus for responding to a request for the transfer of information from another unit by providing any one of up to three signal responses including a positive acknowledge signal indicating an immediate response, a negative acknowledge signal indicating that the unit will most likely be busy for a relatively extended period of time and a quasi-negative response indicating that the unit will probably be ready during the next asynchronously generated bus transfer cycle.
摘要翻译：在具有多个单元的数据处理系统中，在异步生成的信息总线传送周期期间，通过公共电气总线在其间传送信息而耦合，这些单元耦合在优先网络中，并且根据它们各自的优先级可以访问总线在较低优先级的单元被启用之前。每个单元包括用于通过提供包括表示立即响应的肯定确认信号的多达三个信号响应中的任何一个来响应来自另一个单元的信息传送的请求的装置，指示该单元最多的否定确认信号可能在相对延长的时间段内处于忙碌状态，并且产生准负面响应，指示该单元可能在下一个异步生成的总线传输周期期间准备就绪。

22. 发明授权

US3938084A Error detection apparatus for verifying binary coded constants 失效
标题翻译：用于验证二进制编码常数的误差检测装置
公开(公告)号：US3938084A
公开(公告)日：1976-02-10
申请号：US536127
申请日：1974-12-24
申请人： George J. Barlow
发明人： George J. Barlow
IPC分类号： G06F11/08 , G06F11/10 , H03K13/34 , G11B27/36
CPC分类号： G06F11/10 , G06F11/085
摘要： A peripheral subsystem includes error detection apparatus for verifying whether "speed constants" applied thereto have been decoded properly and contain legal codes. The detection apparatus includes binary to decimal decoder circuits which receive the binary coded speed constants and generate a predetermined output signal on one of a plurality of output terminals of the decoder circuits. A selected number of output terminals of the binary to decimal decoder circuits which are less than one half of the total output terminals are applied as inputs to an odd-even check circuit. When each of the constants are decoded without error and contain a legal code, the decoder circuits provide signals to the check circuit which produce a predetermined check signal to indicate that the constant has been decoded properly by the decoder circuits and contains a legal code.
摘要翻译：外围子系统包括用于验证适用于其中的“速度常数”是否已被正确解码并包含合法代码的错误检测装置。检测装置包括二进制到十进制解码器电路，其接收二进制编码速度常数并在解码器电路的多个输出端之一上产生预定的输出信号。小于总输出端子的一半的二进制到十进制解码器电路的选定数量的输出端子被作为奇偶校验电路的输入。当每个常数被解码而没有错误并且包含合法代码时，解码器电路向检查电路提供产生预定检查信号的信号，以指示常数已被解码器电路适当地解码并且包含合法代码。

23. 发明授权

US5850521A Apparatus and method for interprocessor communication 失效
标题翻译：处理器间通信的装置和方法
公开(公告)号：US5850521A
公开(公告)日：1998-12-15
申请号：US689655
申请日：1991-04-23
申请人： Victor M. Morganti , Patrick E. Prange , James B. Geyer , George J. Barlow
发明人： Victor M. Morganti , Patrick E. Prange , James B. Geyer , George J. Barlow
IPC分类号： G06F15/167 , G06F15/17
CPC分类号： G06F15/167 , G06F15/17
摘要： In order to provide communication between two processors in a data processing system, a target processor includes apparatus that can store data signal groups from a source processor. Having stored a data signal group from the source processor, the target processor notifies the source processor of the receipt of the data signal group. In response to the presence of the stored data signal group, the target processor executes a interprocessor command or instruction identified by the transferred data signal group. The source processor at a preselected time, executes an instruction to determine if the command designated by the data signal group stored in the target processor has been executed. The commands specified by the transferred data signal groups can be executed under hardware control by the target processor in a relatively short time immediately following completion of the instruction in execution in the target processor at the time of the transfer of the data signal group. The interprocessor communication has only a minor impact on the performance of the source processor and the target processor because of the command implementation by apparatus.
摘要翻译：为了在数据处理系统中的两个处理器之间提供通信，目标处理器包括可以存储来自源处理器的数据信号组的装置。从源处理器存储了数据信号组后，目标处理器向源处理器通知数据信号组的接收。响应于存储的数据信号组的存在，目标处理器执行由传送的数据信号组识别的处理器间命令或指令。源处理器在预先选择的时间，执行指令，以确定由目标处理器中存储的数据信号组指定的命令是否已被执行。由传送的数据信号组指定的命令可以在目标处理器在数据信号组传送时在目标处理器中执行的指令完成之后的较短时间内由目标处理器在硬件控制下执行。由于设备的命令实现，处理器之间的通信对源处理器和目标处理器的性能影响不大。

24. 发明授权

US5404535A Apparatus and method for providing more effective reiterations of processing task requests in a multiprocessor system 失效
标题翻译：用于在多处理器系统中提供更有效重复处理任务请求的装置和方法
公开(公告)号：US5404535A
公开(公告)日：1995-04-04
申请号：US781524
申请日：1991-10-22
申请人： George J. Barlow , James W. Keeley
发明人： George J. Barlow , James W. Keeley
IPC分类号： G06F9/46 , G06F13/24 , G06F13/26 , G06F15/16 , G06F15/17 , G06F15/177
CPC分类号： G06F13/24 , G06F13/26 , G06F15/17
摘要： A multiprocessor computer system having a first processor having a first interrupt mechanism for generating interrupt requests, a second processor having a second interrupt mechanism, and a system bus for communicating interrupt requests from the first processor to the second processor. The second interrupt mechanism is responsive to an interrupt request by generating an acknowledge response on the system bus when the second processor accepts the interrupt request and generating a not acknowledge response on the system bus when the second processor contains a previous and pending interrupt request of higher level and refuses the interrupt request. The second interrupt mechanism is responsive to the completion of servicing of an interrupt request by the second processor by placing on the system bus an interrupt completed command, which includes an address identifying the second processor and a code indicating that the second processor has completing servicing an interrupt request. The first processor includes an interrupt retry means, which includes a refused interrupt register means responsive to a not acknowledge response from the second processor in response to an interrupt requested from the first processor for storing the channel number of the second processor, and level monitor logic connected from the system bus.
摘要翻译：一种具有第一处理器的多处理器计算机系统，具有用于产生中断请求的第一中断机制，具有第二中断机制的第二处理器和用于将来自第一处理器的中断请求传送到第二处理器的系统总线。第二中断机制响应于中断请求，当第二处理器接收到中断请求并且当第二处理器包含较高的先前和未决中断请求时，在系统总线上产生不确认响应时，通过在系统总线上产生确认响应级别并拒绝中断请求。第二中断机制响应于由第二处理器完成对中断请求的完成，通过在系统总线上放置一个中断完成命令，该命令包括标识第二处理器的地址和指示第二处理器完成服务的代码中断请求。第一处理器包括中断重试装置，其包括响应于从第一处理器请求的用于存储第二处理器的信道号的中断响应来自第二处理器的不确认响应的拒绝中断寄存器装置，以及级别监视器逻辑从系统总线连接。

25. 发明授权

US5379378A Data processing system having a bus command generated by one subsystem on behalf of another subsystem 失效
标题翻译：数据处理系统具有由一个子系统代表另一子系统产生的总线命令
公开(公告)号：US5379378A
公开(公告)日：1995-01-03
申请号：US773752
申请日：1991-10-10
申请人： Arthur Peters , Richard C. Zelley , Elmer W. Carroll , George J. Barlow , Chester M. Nibby, Jr. , James W. Keeley
发明人： Arthur Peters , Richard C. Zelley , Elmer W. Carroll , George J. Barlow , Chester M. Nibby, Jr. , James W. Keeley
IPC分类号： G06F13/362 , G06F13/26 , G06F13/38 , G06F13/42 , G06F15/16
CPC分类号： G06F13/4243
摘要： A data processing system includes a system management unit, a number of central subsystems, a main memory and a number of peripheral subsystems all coupled in common to a system bus. Any subsystem may generate a command which includes a first field specifying a destination subsystem, a second field specifying the operation the destination subsystem is to perform. If a response is required, the subsystem generating the initial command may specify a third subsystem for receiving the response command.
摘要翻译：数据处理系统包括系统管理单元，多个中央子系统，主存储器和多个共同连接到系统总线的外围子系统。任何子系统可以生成包括指定目的地子系统的第一字段的命令，指定目的地子系统要执行的操作的第二字段。如果需要响应，则生成初始命令的子系统可以指定用于接收响应命令的第三子系统。

26. 发明授权

US5210757A Method and apparatus for performing health tests of units of a data processing system 失效
标题翻译：用于对数据处理系统的单元执行健康测试的方法和装置
公开(公告)号：US5210757A
公开(公告)日：1993-05-11
申请号：US593408
申请日：1990-10-05
申请人： George J. Barlow , Richard C. Zelley , James W. Keeley
发明人： George J. Barlow , Richard C. Zelley , James W. Keeley
IPC分类号： G06F11/00 , G06F11/22 , G06F11/273
CPC分类号： G06F11/22 , G06F11/2736 , G06F11/0757
摘要： A means for ascertaining the health, or basic operational status, of a system unit. A "health check" provides an indication of either "yes", the system unit is operational, or "no", the system unit is either inoperative or there is a question as to whether the system is operational. The test is performed by requesting that the system unit perform a high priority "short" operation and noting the response provided to the request; the actual execution of the request is unimportant and it is the response of the unit under test to the receipt of the request for a bus operation that is the actual indicator of the status of the unit being tested. The requested operation is not directed at the unit whose operational status is to be determined, but instead at a bus interface unit which performs bus operations for the unit to be tested and whose responses to requests for bus operations are effected by the operational status of the unit that is to be tested. The operation is not directed at an actual element in the bus interface unit, but at a phantom, or nonexistent, element.
摘要翻译：一种用于确定系统单元的健康或基本操作状态的方法。 “健康检查”提供“是”，系统单元运行或“否”的指示，系统单元不工作或者是否存在系统是否可操作的问题。通过请求系统单元执行高优先级“短”操作并注意提供给请求的响应来执行测试; 请求的实际执行不重要，并且是接收到总线操作请求的被测单元的响应，该总线操作是正在测试的单元的状态的实际指示符。所请求的操作不是针对要确定其操作状态的单元，而是指向执行待测单元的总线操作的总线接口单元，并且其对总线操作请求的响应由要测试的单位该操作不是针对总线接口单元中的实际元件，而是以幻像或不存在的元素。

27. 发明授权

US5204964A Method and apparatus for resetting a memory upon power recovery 失效
标题翻译：电源恢复时重置存储器的方法和装置
公开(公告)号：US5204964A
公开(公告)日：1993-04-20
申请号：US593917
申请日：1990-10-05
申请人： Raymond D. Bowden, III , Michelle A. Pence , George J. Barlow , Marc E. Sanfacon , Jeffrey S. Somers
发明人： Raymond D. Bowden, III , Michelle A. Pence , George J. Barlow , Marc E. Sanfacon , Jeffrey S. Somers
IPC分类号： G06F11/14 , G06F11/20 , G11C7/20 , G11C11/406
CPC分类号： G06F11/1441 , G11C11/406 , G11C7/20 , G06F11/2015
摘要： A method and apparatus for resetting memory state when power is applied to the system. The memory has memory elements, a refresh clock and a refresh counter for counting refresh cycles and providing refresh signals to the memory elements, the memory elements and refresh means being connected from the power system and from a battery back-up means. A state detection means is connected from the refresh counter for detecting a change in state of the refresh counter to a state equivalent to the reset state of the refresh counter and asserting a state change signal. A means responsive to the state change signal and to the occurrence of the reset signal provides a memory controller reset signal, so that the memory controller reset signal occurs in synchronization with the change of state of the refresh counter to a state equivalent to the refresh counter reset state. The memory reset further includes a time-out counter means responsive to the assertion of the reset signal and to the refresh clock for counting refresh cycles in synchronization with the refresh counter. A time-out detection means is responsive to the time out counter means for providing a time out signal when the time-out counter has counted a refresh period plus one clock cycle and to the state change signal for providing the memory controller reset signal when the time-out counter has counted a refresh cycle plus one clock period and the state change signal has not been asserted.
摘要翻译：一种当向系统施加电力时复位存储器状态的方法和装置。存储器具有存储器元件，刷新时钟和刷新计数器，用于对刷新周期进行计数，并向存储器元件提供刷新信号，存储器元件和刷新装置从电力系统和电池备用装置连接。状态检测装置从刷新计数器连接，用于检测刷新计数器的状态改变到与刷新计数器的复位状态相当的状态，并且断言状态改变信号。响应于状态改变信号和复位信号的发生的装置提供存储器控制器复位信号，使得存储器控制器复位信号与刷新计数器的状态改变同步到与刷新计数器相当的状态复位状态。存储器复位还包括响应于重置信号的断言和与刷新计数器同步来刷新周期的刷新时钟的超时计数器装置。超时检测装置响应于超时计数器装置，用于当超时计数器已经计数了刷新周期加一个时钟周期时提供超时信号，以及当状态改变信号提供存储器控制器复位信号时超时计数器已经计数了刷新周期加上一个时钟周期，状态改变信号还没有被断言。

28. 发明授权

US5193181A Recovery method and apparatus for a pipelined processing unit of a multiprocessor system 失效
标题翻译：多处理器系统管道处理单元的恢复方法和装置
公开(公告)号：US5193181A
公开(公告)日：1993-03-09
申请号：US593458
申请日：1990-10-05
申请人： George J. Barlow , James W. Keeley , Richard A. Lemay , Jian-Kuo Shen , Robert V. Ledoux, deceased , Thomas F. Joyce , Richard P. Kelly , Robert C. Miller
发明人： George J. Barlow , James W. Keeley , Richard A. Lemay , Jian-Kuo Shen , Robert V. Ledoux, deceased , Thomas F. Joyce , Richard P. Kelly , Robert C. Miller
IPC分类号： G06F11/00 , G06F11/22
CPC分类号： G06F11/0793 , G06F11/0724 , G06F11/0766 , G06F11/004 , G06F11/2205
摘要： The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode. Control circuits execute a UEV handler microcode routine which reads the contents of syndrome registers included on each board containing the UEV indicator states in addition to error signals into register file working locations. The UEV signal is then cleared enabling the BIU to resume communications with the sytem bus.

29. 发明授权

US5150466A Flexible distributed bus priority network 失效
标题翻译：灵活的分布式总线优先网络
公开(公告)号：US5150466A
公开(公告)日：1992-09-22
申请号：US593436
申请日：1990-10-05
申请人： George J. Barlow , Donald L. Smith
发明人： George J. Barlow , Donald L. Smith
IPC分类号： G06F13/37
CPC分类号： G06F13/37
摘要： A multiprocessor system includes a system management facility (SMF) unit, a plurality of central subsystem (CSS) units, a plurality of memory subsystem units and first and second pluralities of input/output units which connect in common to a system bus. Requests are transferred between a pair of units on a distributed bus priority network included as part of the system bus on the basis of the unit's physical position on the bus relative to one end of the bus. The SMF unit positioned at the high priority end of the bus includes fast recovery bus request logic circuits which connect to the high priority request line of the priority network. Each of the CSS units positioned after the SMF unit on either side of the memory subsystems includes bus request logic circuits which connect only to the low priority request line. The memory subsystems each include bus request logic circuits which connect to both the high and low priority request lines for accepting and granting cycles from higher and lower priority units. This enables the positioning of the first and second pluralities of input/output units positioned below the memory subsystems to operate as high and low priority requestors.
摘要翻译：多处理器系统包括系统管理设备（SMF）单元，多个中央子系统（CSS）单元，多个存储器子系统单元以及共同连接到系统总线的第一和第二多个输入/输出单元。在基于总线上相对于总线一端的总线上的物理位置的基础上，在作为系统总线的一部分的分布式总线优先级网络上的一对单元之间传送请求。位于总线高优先级端的SMF单元包括连接到优先级网络的高优先级请求线路的快速恢复总线请求逻辑电路。位于存储器子系统两侧的SMF单元之后的每个CSS单元包括仅连接到低优先级请求线的总线请求逻辑电路。存储器子系统各自包括连接到高优先级请求线和低优先级请求线的总线请求逻辑电路，用于接受和授予来自较高和较低优先级的单元的周期。这使得能够定位位于存储器子系统下方的第一和第二多个输入/输出单元作为高优先级和低优先权请求者来操作。

30. 发明授权

US4910666A Apparatus for loading and verifying a control store memory of a central subsystem 失效
标题翻译：用于加载和验证中央子系统的控制存储器的装置
公开(公告)号：US4910666A
公开(公告)日：1990-03-20
申请号：US943984
申请日：1986-12-18
申请人： Chester M. Nibby, Jr. , Richard C. Zelley , Kenneth E. Bruce , George J. Barlow , James W. Keeley
发明人： Chester M. Nibby, Jr. , Richard C. Zelley , Kenneth E. Bruce , George J. Barlow , James W. Keeley
IPC分类号： G06F9/445 , G06F9/22 , G06F9/24
CPC分类号： G06F9/24
摘要： A central subsystem of a data processing system includes a writable control store which is loaded with firmware to control the central subsystem operations. The central subsystem logic is responsive to a sequence of commands from a system management facility to load the control store and verify that the control store firmware is loaded correctly.

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