专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20050101110A1 Novel method to reduce the fluorine contamination on the Al/Al-Cu pad by a post high cathod temperature plasma treatment 失效
标题翻译：通过后期高阴极温度等离子体处理来减少Al / Al-Cu焊盘上的氟污染的新方法
公开(公告)号：US20050101110A1
公开(公告)日：2005-05-12
申请号：US10706382
申请日：2003-11-12
申请人： Wen-Jui Fu , Shang-Ru Sheu , Yun-Hung Shen , Chao-Cheng Chen
发明人： Wen-Jui Fu , Shang-Ru Sheu , Yun-Hung Shen , Chao-Cheng Chen
IPC分类号： H01L21/306 , H01L21/311 , H01L21/322 , H01L21/44
CPC分类号： H01L21/31116 , H01L21/02046
摘要： A method of reducing fluorine contamination on a integrated circuit wafer surface is achieved. The method comprises placing an integrated circuit wafer on a cathode stage. The integrated circuit wafer comprises a surface contaminated with fluorine. The integrated circuit wafer is plasma treated with a plasma comprising a reducing gas that forms HF from the fluorine and a bombardment gas that removes the fluorine from the surface. The cathode stage is heated to thereby increase the rate of the fluorine removal.
摘要翻译：实现了降低集成电路晶片表面上的氟污染的方法。该方法包括将集成电路晶片放置在阴极级上。集成电路晶片包括被氟污染的表面。集成电路晶片用包括从氟形成HF的还原气体的等离子体等离子体处理，以及从表面除去氟的轰击气体。加热阴极级，从而提高除氟率。

22. 发明授权

US06383943B1 Process for improving copper fill integrity 有权
标题翻译：改善铜填充完整性的工艺
公开(公告)号：US06383943B1
公开(公告)日：2002-05-07
申请号：US09687160
申请日：2000-10-16
申请人： Chao-Cheng Chen , Jen-Cheng Liu , Jyu-Horng Shieh , Chia-Shiung Tsai , Bor-Shyang Lin
发明人： Chao-Cheng Chen , Jen-Cheng Liu , Jyu-Horng Shieh , Chia-Shiung Tsai , Bor-Shyang Lin
IPC分类号： H01L21302
CPC分类号： H01L21/76843 , H01L21/3105 , H01L21/76802 , H01L21/76814 , H01L21/76826 , H01L21/76829
摘要： A method for eliminating the problems associated with the discontinuous deposition of the glue layer at the bottom of the via resulting from the notch in the silicon nitride etch stop layer. First conductive layer traces are patterned and a silicon nitride (SiN) etch stop layer is provided overlying the first conductive layer. An inter-metal dielectric (IMD) layer then overlies the entire surface. An anisotropic etch is performed leaving via holes in the IMD layer. This is followed by a second anisotropic etch step to remove the etch stop layer not protected by the IMD layer resulting in the formation a notch at the bottom of the via hole. An important step of the present invention is the elimination of this notch accomplished by nitridizing the surface of the IMD layer. A wet polymer cleaning is performed to remove the nitridized IMD surface and eliminating the notch. A glue layer is conformally applied lining the via hole. A second conductive layer is then deposited and the surface is planarized.
摘要翻译：一种用于消除与在氮化硅蚀刻停止层中由凹口产生的通孔底部的胶层不连续沉积相关的问题的方法。图案化第一导电层迹线，并且覆盖第一导电层提供氮化硅（SiN）蚀刻停止层。金属间电介质（IMD）层然后覆盖整个表面。进行各向异性蚀刻，留下IMD层中的通孔。然后进行第二个各向异性蚀刻步骤以去除不被IMD层保护的蚀刻停止层，从而在通孔的底部形成切口。本发明的重要步骤是消除通过使IMD层的表面氮化而实现的这个缺口。执行湿式聚合物清洁以除去氮化的IMD表面并消除凹口。粘合层适用于衬套通孔。然后沉积第二导电层并且将表面平坦化。

23. 发明授权

US06297168B1 Edge defect inhibited trench etch plasma etch method 有权
标题翻译：边缘缺陷抑制沟槽蚀刻等离子体蚀刻方法
公开(公告)号：US06297168B1
公开(公告)日：2001-10-02
申请号：US09677068
申请日：2000-09-29
申请人： Jyu-Horng Shieh , Jen-Cheng Liu , Chao-Cheng Chen , Li-Chi Chao , Chia-Shia Tsai
发明人： Jyu-Horng Shieh , Jen-Cheng Liu , Chao-Cheng Chen , Li-Chi Chao , Chia-Shia Tsai
IPC分类号： H01L213065
CPC分类号： H01L21/7681 , H01L21/31116
摘要： Within a method for etching a trench within a silicon oxide layer there is first provided a substrate. There is then formed over the substrate a silicon oxide layer. There is then formed over the silicon oxide layer a masking layer. There is then etched, while employing a plasma etch method in conjunction with the masking layer as an etch mask layer, the silicon oxide layer to form an etched silicon oxide layer defining a trench. Within the method, the plasma etch method employs an etchant gas composition comprising: (1) octafluorocyclobutane; and (2) at least one of carbon tetrafluoride, difluoromethane, hexafluoroethane and oxygen; but excluding (3) a carbon and oxygen containing gas.
摘要翻译：在氧化硅层内蚀刻沟槽的方法中，首先提供衬底。然后在衬底上形成氧化硅层。然后在氧化硅层上形成掩模层。然后蚀刻，同时使用等离子体蚀刻方法结合掩模层作为蚀刻掩模层，氧化硅层形成蚀刻氧化硅层，限定沟槽。在该方法中，等离子体蚀刻方法采用蚀刻剂气体组合物，其包含：（1）八氟环丁烷; 和（2）四氟化碳，二氟甲烷，六氟乙烷和氧中的至少一种; 但不包括（3）含碳和含氧气体。

24. 发明授权

US06277752B1 Multiple etch method for forming residue free patterned hard mask layer 有权
标题翻译：用于形成无残留的图案化硬掩模层的多次蚀刻方法
公开(公告)号：US06277752B1
公开(公告)日：2001-08-21
申请号：US09342040
申请日：1999-06-28
申请人： Chao-Cheng Chen
发明人： Chao-Cheng Chen
IPC分类号： H01L21302
CPC分类号： H01L21/76224 , H01L21/3081
摘要： A method for forming a patterned hard mask layer. There is first provided a substrate. There is then formed over the substrate a blanket hard mask layer formed of a hard mask material susceptible to etching within a first plasma etch method, where the first plasma etch method employs a first etchant gas composition which upon plasma activation forms an active fluorine containing etchant species. There is then formed over the blanket hard mask layer a patterned photoresist layer. There is then etched, while employing the first plasma etch method in conjunction with the patterned photoresist layer as a first etch mask layer, the blanket hard mask layer to form a patterned hard mask layer which defines a first aperture. The first plasma etch method also forms at the bottom of the first aperture defined by the patterned hard mask layer a residue. Finally, there is then etched, while employing a second etch method, the residue from the bottom of the first aperture. The patterned hard mask layer may then be employed for forming within a microelectronic layer, such as a semiconductor substrate, formed beneath the microelectronic layer, an aperture, such as an isolation trench, while employing a third plasma etch method. There may then be formed within the aperture a planarized aperture fill layer, such as a planarized trench isolation region, with enhanced planarity.
摘要翻译：一种形成图案化硬掩模层的方法。首先提供基板。然后在衬底上形成由在第一等离子体蚀刻方法中容易蚀刻的硬掩模材料形成的橡皮布硬掩模层，其中第一等离子体蚀刻方法采用第一蚀刻剂气体组合物，其在等离子体激活时形成活性含氟蚀刻剂种类。然后在橡皮布硬掩模层上形成图案化的光致抗蚀剂层。然后蚀刻，同时采用第一等离子体蚀刻方法结合图案化的光致抗蚀剂层作为第一蚀刻掩模层，橡皮布硬掩模层以形成限定第一孔的图案化硬掩模层。第一等离子体蚀刻方法也形成在由图案化的硬掩模层限定的第一孔的底部残留物处。最后，然后在使用第二蚀刻方法的同时蚀刻来自第一孔径底部的残留物。然后可以使用图案化的硬掩模层，在采用第三等离子体蚀刻方法的同时，在微电子层（例如形成在微电子层下方的半导体衬底），孔（例如隔离沟槽）之间形成。然后可以在孔内形成具有增强的平面度的平坦化孔填充层，例如平坦化的沟槽隔离区域。

25. 发明授权

US6040248A Chemistry for etching organic low-k materials 失效
标题翻译：化学蚀刻有机低k材料
公开(公告)号：US6040248A
公开(公告)日：2000-03-21
申请号：US104032
申请日：1998-06-24
申请人： Chao-Cheng Chen , Ming-Hsin Huang , Hun-Jan Tao , Chia-Shiung Tsai
发明人： Chao-Cheng Chen , Ming-Hsin Huang , Hun-Jan Tao , Chia-Shiung Tsai
IPC分类号： H01L21/311 , H01L21/768 , H01L21/302 , C23F1/02 , H01L21/461
CPC分类号： H01L21/31138 , H01L21/76802
摘要： A process for plasma etching of contact and via openings in low-k organic polymer dielectric layers is described which overcomes problems of sidewall bowing and hardmask pattern deterioration by etching the organic layer in a high density plasma etcher with a chlorine/inert gas plasma. By adding chlorine to the oxygen/inert gas plasma, the development of an angular aspect or faceting of the hardmask pattern edges by ion bombardment is abated. Essentially vertical sidewalls are obtained in the openings etched in the organic polymer layer while hardmask pattern integrity is maintained. The addition of a passivating agent such as nitrogen, BCl.sub.3, or CHF.sub.3 to the etchant gas mixture further improves the sidewall profile by reducing bowing through protective polymer formation.
摘要翻译：描述了一种用于等离子体蚀刻低k有机聚合物介电层中的接触和通孔开口的方法，其通过用氯/惰性气体等离子体在高密度等离子体蚀刻机中蚀刻有机层来克服侧壁弯曲和硬掩模图案劣化的问题。通过向氧/惰性气体等离子体中加入氯，减少了通过离子轰击形成硬掩模图案边缘的角度方面或刻面。在保持硬掩模图案完整性的同时，在有机聚合物层中蚀刻的开口中获得基本垂直的侧壁。钝化剂如氮气，BCl3或CHF3添加到蚀刻剂气体混合物中，通过减少通过保护性聚合物形成的弯曲来进一步改善侧壁轮廓。

26. 发明授权

US09991375B2 Metal gate electrode of a semiconductor device 有权
公开(公告)号：US09991375B2
公开(公告)日：2018-06-05
申请号：US13484047
申请日：2012-05-30
申请人： Jr-Jung Lin , Chih-Han Lin , Jin-Aun Ng , Ming-Ching Chang , Chao-Cheng Chen
发明人： Jr-Jung Lin , Chih-Han Lin , Jin-Aun Ng , Ming-Ching Chang , Chao-Cheng Chen
IPC分类号： H01L29/78 , H01L21/283 , H01L29/49 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/78 , H01L21/283 , H01L21/823842 , H01L29/4966 , H01L29/4983 , H01L29/66545
摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode.

27. 发明授权

US09595443B2 Metal gate structure of a semiconductor device 有权
标题翻译：半导体器件的金属栅极结构
公开(公告)号：US09595443B2
公开(公告)日：2017-03-14
申请号：US13277642
申请日：2011-10-20
申请人： Ming Zhu , Hui-Wen Lin , Harry-Hak-Lay Chuang , Bao-Ru Young , Yuan-Sheng Huang , Ryan Chia-Jen Chen , Chao-Cheng Chen , Kuo-Cheng Ching , Ting-Hua Hsieh , Carlos H. Diaz
发明人： Ming Zhu , Hui-Wen Lin , Harry-Hak-Lay Chuang , Bao-Ru Young , Yuan-Sheng Huang , Ryan Chia-Jen Chen , Chao-Cheng Chen , Kuo-Cheng Ching , Ting-Hua Hsieh , Carlos H. Diaz
IPC分类号： H01L21/70 , H01L21/28 , H01L21/8234 , H01L29/49 , H01L29/66 , H01L29/423
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/823437 , H01L21/82345 , H01L21/823475 , H01L21/823481 , H01L29/42376 , H01L29/4966
摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.
摘要翻译：本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括：衬底，包括围绕并分离P活性区域和N-有源区域的隔离区域; 在P-活性区域上的P金属栅电极，并且在隔离区域上延伸，其中P金属栅电极包括P功函数金属和P功函数金属与衬底之间的含氧TiN层; 以及N型金属栅电极，其在N-有源区上方并在隔离区上方延伸，其中N型金属栅电极包括N功函数金属和N功函数金属与衬底之间的富氮TiN层其中富氮TiN层在隔离区域上连接到含氧TiN层。

28. 发明授权

US09355874B2 Silicon nitride etching in a single wafer apparatus 有权
标题翻译：在单晶片装置中进行氮化硅蚀刻
公开(公告)号：US09355874B2
公开(公告)日：2016-05-31
申请号：US13244337
申请日：2011-09-24
申请人： Weibo Yu , Hsueh-Chin Lu , Han-Guan Chew , Kuo Bin Huang , Chao-Cheng Chen , Syun-Ming Jang
发明人： Weibo Yu , Hsueh-Chin Lu , Han-Guan Chew , Kuo Bin Huang , Chao-Cheng Chen , Syun-Ming Jang
IPC分类号： C03C15/00 , H01L21/67 , H01L21/311
CPC分类号： H01L21/6708 , H01L21/31111
摘要： A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride layer in a single wafer etching apparatus includes: heating a phosphoric acid to a first temperature; heating a sulfuric acid to a second temperature; mixing the heated phosphoric acid and the heated sulfuric acid; heating the phosphoric acid/sulfuric acid mixture to a third temperature; and etching the silicon nitride layer with the heated phosphoric acid/sulfuric acid mixture.
摘要翻译：公开了在单晶片蚀刻装置中实现的单晶片蚀刻装置和各种方法。在一个实施例中，在单晶片蚀刻装置中蚀刻氮化硅层包括：将磷酸加热至第一温度; 将硫酸加热至第二温度; 混合加热的磷酸和加热的硫酸; 将磷酸/硫酸混合物加热至第三温度; 并用加热的磷酸/硫酸混合物蚀刻氮化硅层。

29. 发明授权

US08932936B2 Method of forming a FinFET device 有权
标题翻译：形成FinFET器件的方法
公开(公告)号：US08932936B2
公开(公告)日：2015-01-13
申请号：US13449118
申请日：2012-04-17
申请人： Chia-Chu Liu , Kuei-Shun Chen , Chih-Hsiung Peng , Chi-Kang Chang , Chiang Mu-Chi , Sheng-Yu Chang , Hua Feng Chen , Chao-Cheng Chen , Ryan Chia-Jen Chen
发明人： Chia-Chu Liu , Kuei-Shun Chen , Chih-Hsiung Peng , Chi-Kang Chang , Chiang Mu-Chi , Sheng-Yu Chang , Hua Feng Chen , Chao-Cheng Chen , Ryan Chia-Jen Chen
IPC分类号： H01L21/00
CPC分类号： H01L21/3086 , H01L21/76224
摘要： A method for fabricating a device is disclosed. An exemplary method includes providing a substrate and forming a plurality of fins over the substrate. The method further includes forming a first opening in the substrate in a first longitudinal direction. The method further includes forming a second opening in the substrate in a second longitudinal direction. The first and second longitudinal directions are different. The method further includes depositing a filling material in the first and second openings.
摘要翻译：公开了一种制造装置的方法。一种示例性的方法包括提供衬底并在衬底上形成多个鳍。该方法还包括在第一纵向方向上在基板中形成第一开口。该方法还包括在第二纵向方向上在基板中形成第二开口。第一和第二纵向是不同的。该方法还包括在第一和第二开口中沉积填充材料。

30. 发明申请

US20130187235A1 COMPOSITE DUMMY GATE WITH CONFORMAL POLYSILICON LAYER FOR FINFET DEVICE 有权
标题翻译：用于FINFET器件的具有合成多晶硅层的复合绝缘栅
公开(公告)号：US20130187235A1
公开(公告)日：2013-07-25
申请号：US13353975
申请日：2012-01-19
申请人： Yuan-Sheng Huang , Tzu-Yen Hsieh , Ming-Ching Chang , Chao-Cheng Chen , Chia-Jen Chen
发明人： Yuan-Sheng Huang , Tzu-Yen Hsieh , Ming-Ching Chang , Chao-Cheng Chen , Chia-Jen Chen
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L27/0924 , H01L29/0649 , H01L29/66795 , H01L29/785
摘要： The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.
摘要翻译：本公开涉及FinFET。 FinFET包括在衬底上形成的翅片结构。栅介质层最少部分地缠绕在翅片结构的一段上。栅介质层包含高k栅介质材料。 FinFET包括在栅介质层上共形形成的多晶硅层。 FinFET包括在多晶硅层上形成的金属栅极电极层。本公开提供了制造FinFET的方法。该方法包括提供包含半导体材料的翅片结构。该方法包括在鳍结构上方形成栅极电介质层，栅介质层至少部分地围绕翅片结构缠绕。该方法包括在栅介质层上形成多晶硅层，其中多晶硅层以保形方式形成。该方法包括在多晶硅层上形成伪栅极层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式