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21. 发明授权

US09437257B2 Sensing circuit, memory device and data detecting method 有权
标题翻译：感应电路，存储器和数据检测方法
公开(公告)号：US09437257B2
公开(公告)日：2016-09-06
申请号：US13765513
申请日：2013-02-12
申请人： Tien-Chun Yang , Yue-Der Chih , Chan-Hong Chern , Tao Wen Chung
发明人： Tien-Chun Yang , Yue-Der Chih , Chan-Hong Chern , Tao Wen Chung
IPC分类号： G11C11/34 , G11C7/00 , G11C7/02 , G11C7/06 , G11C7/14 , G11C13/00
CPC分类号： G11C7/062 , G11C7/14 , G11C13/004 , G11C2207/063
摘要： A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage.
摘要翻译：感测电路包括感测电阻器，参考电阻器和比较器。比较器具有耦合到感测电阻器的第一输入端，耦合到参考电阻器的第二输入端和输出端。第一输入被配置为耦合到与存储器单元相关联的数据位线，以接收由流过感测电阻器的存储单元的单元电流引起的感测输入电压。第二输入被配置为耦合到与参考单元相关联的参考位线，以接收由参考电池流过参考电阻器的参考电流引起的感测参考电压。比较器被配置为基于感测输入电压和感测参考电压之间的比较，在输出处产生指示存储在存储器单元中的数据的逻辑状态的输出信号。

22. 发明授权

US08228221B2 Method and apparatus for calibrating sigma-delta modulator 有权
标题翻译：用于校准Σ-Δ调制器的方法和装置
公开(公告)号：US08228221B2
公开(公告)日：2012-07-24
申请号：US12891952
申请日：2010-09-28
申请人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin , Manoj M. Mhala , Tao Wen Chung , Chin-Hao Chang
发明人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin , Manoj M. Mhala , Tao Wen Chung , Chin-Hao Chang
IPC分类号： H03M3/02
CPC分类号： H03M3/38 , H03M3/414
摘要： In a method of converting an analog signal to digital format, an analog input signal is received and processed using sigma-delta modulation to provide a first digital signal that represents the analog input signal in digital format and to provide a second digital signal that represents a first error introduced during the sigma-delta modulation. A second error that is error introduced during the sigma-delta modulation is estimated. A pre-correction signal is determined based on the first and second digital signals. A difference between the estimated second error and the pre-correction digital signal is determined to provide a digital output signal representing the analog input signal in digital format. An error correction element operable to adjust the digital output signal based on the analog input signal, the digital output signal, and the second digital signal is controlled.
摘要翻译：在将模拟信号转换为数字格式的方法中，使用Σ-Δ调制接收和处理模拟输入信号，以提供表示数字格式的模拟输入信号的第一数字信号，并提供表示第在Σ-Δ调制期间引入的第一个误差。估计在Σ-Δ调制期间引入误差的第二个误差。基于第一和第二数字信号确定预校正信号。确定估计的第二误差和预校正数字信号之间的差异以提供表示数字格式的模拟输入信号的数字输出信号。控制基于模拟输入信号，数字输出信号和第二数字信号来调整数字输出信号的纠错元件。

23. 发明授权

US08957482B2 Electrical fuse and related applications 有权
标题翻译：电熔丝及相关应用
公开(公告)号：US08957482B2
公开(公告)日：2015-02-17
申请号：US12731325
申请日：2010-03-25
申请人： Fu-Lung Hsueh , Tao Wen Chung , Po-Yao Ke , Shine Chung
发明人： Fu-Lung Hsueh , Tao Wen Chung , Po-Yao Ke , Shine Chung
IPC分类号： H01L23/62 , H01L27/06 , H01L23/525 , H01L27/112 , H01L27/10 , H01L29/78
CPC分类号： H01L23/5256 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L29/785 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In various embodiments, the fuse is formed from silicide and on top of a fin of a fin structure. Because the fuse is formed on top of a fin, its width takes the width of the fin, which is very thin. Depending on implementations, the fuse is also formed using planar technology and includes a thin width. Because the width of the fuse is relatively thin, a predetermined current can reliably cause the fuse to be opened. Further, the fuse can be used with a transistor to form a memory cell used in memory arrays, and the transistor utilizes FinFET technology.
摘要翻译：在各种实施例中，熔丝由硅化物形成，并且在翅片结构的翅片的顶部上形成。因为熔丝形成在翅片的顶部，所以它的宽度取得了非常薄的翅片的宽度。根据实施方案，保险丝也使用平面技术形成并且包括薄的宽度。因为保险丝的宽度较薄，所以能够可靠地使保险丝断开。此外，熔丝可以与晶体管一起使用以形成用于存储器阵列的存储单元，并且晶体管利用FinFET技术。

24. 发明授权

US08279102B2 Method and apparatus for analog to digital conversion 有权
标题翻译：用于模数转换的方法和装置
公开(公告)号：US08279102B2
公开(公告)日：2012-10-02
申请号：US12898261
申请日：2010-10-05
申请人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin , Manoj M. Mhala , Tao Wen Chung , Chin-Hao Chang
发明人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin , Manoj M. Mhala , Tao Wen Chung , Chin-Hao Chang
IPC分类号： H03M1/38
CPC分类号： H03M1/1215 , H03M1/164 , H03M1/442
摘要： An analog to digital converter (ADC) comprises an input node having a variable analog input voltage, first and second switched capacitor circuits, an operational amplifier, and a control circuit. The first switched capacitor circuit has first and second capacitors and is coupled to the input node, and the second switched capacitor circuit has third and fourth capacitors and is coupled to the input node. The operational amplifier is configured to be conditionally coupled to only one of the first and second switched capacitor circuits at a time and configured to conditionally provide feedback to the switched capacitor circuits via an output node. The control circuit is coupled to the first and second switched capacitor circuits for conditional coupling to the operational amplifier.
摘要翻译：模数转换器（ADC）包括具有可变模拟输入电压的输入节点，第一和第二开关电容器电路，运算放大器和控制电路。第一开关电容器电路具有第一和第二电容器并且耦合到输入节点，并且第二开关电容器电路具有第三和第四电容器并且耦合到输入节点。运算放大器被配置为一次有条件地耦合到第一和第二开关电容器电路中的一个，并且被配置为通过输出节点有条件地向开关电容器电路提供反馈。控制电路耦合到第一和第二开关电容器电路以用于与运算放大器的条件耦合。

25. 发明申请

US20100301453A1 High-Voltage BJT Formed Using CMOS HV Processes 有权
标题翻译：使用CMOS HV工艺形成高压BJT
公开(公告)号：US20100301453A1
公开(公告)日：2010-12-02
申请号：US12750503
申请日：2010-03-30
申请人： Tao Wen Chung , Po-Yao Ke , Wei-Yang Lin , Shine Chung
发明人： Tao Wen Chung , Po-Yao Ke , Wei-Yang Lin , Shine Chung
IPC分类号： H01L27/082
CPC分类号： H01L27/0823 , H01L29/0692 , H01L29/0821 , H01L29/7322 , H01L29/735
摘要： An integrated circuit device includes a semiconductor substrate having a top surface; at least one insulation region extending from the top surface into the semiconductor substrate; a plurality of base contacts of a first conductivity type electrically interconnected to each other; and a plurality of emitters and a plurality of collectors of a second conductivity type opposite the first conductivity type. Each of the plurality of emitters, the plurality of collectors, and the plurality of base contacts is laterally spaced apart from each other by the at least one insulation region. The integrated circuit device further includes a buried layer of the second conductivity type in the semiconductor substrate, wherein the buried layer has an upper surface adjoining bottom surfaces of the plurality of collectors.
摘要翻译：集成电路器件包括具有顶表面的半导体衬底; 至少一个绝缘区域，从所述顶表面延伸到所述半导体衬底中; 多个彼此电互连的第一导电类型的基座触头; 以及与第一导电类型相反的第二导电类型的多个发射极和多个集电极。多个发射器，多个集光器和多个基座触点中的每一个通过至少一个绝缘区域彼此横向间隔开。集成电路装置还包括在半导体衬底中的第二导电类型的掩埋层，其中掩埋层具有邻接多个集电极的底表面的上表面。

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