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1. 发明授权

US08416105B2 ADC calibration apparatus 有权
标题翻译： ADC校准装置
公开(公告)号：US08416105B2
公开(公告)日：2013-04-09
申请号：US13029754
申请日：2011-02-17
申请人： Fang-Shi Jordan Lai , Chin-Hao Chang , Manoj M. Mhala , Hsu-Feng Hsueh , Yung-Fu Lin , Cheng Yen Weng
发明人： Fang-Shi Jordan Lai , Chin-Hao Chang , Manoj M. Mhala , Hsu-Feng Hsueh , Yung-Fu Lin , Cheng Yen Weng
IPC分类号： H03M1/10
CPC分类号： H03M1/1061 , H03M1/361
摘要： An analog-to-digital (ADC) calibration apparatus comprises a calibration buffer, a comparator and a digital calibration block. Each reference voltage is sent to a track-and-hold amplifier as well as the calibration buffer. The comparator compares the output from the track-and-hold amplifier and the output from the calibration buffer and generates a binary number. Based upon a successive approximation method, the digital calibration block finds a correction voltage for ADC offset and nonlinearity compensation. By employing the ADC calibration apparatus, each reference voltage can be calibrated and the corresponding correction voltage can be used to modify the reference voltage during an ADC process.
摘要翻译：模数（ADC）校准装置包括校准缓冲器，比较器和数字校准块。每个参考电压被发送到跟踪和保持放大器以及校准缓冲器。比较器比较跟踪和保持放大器的输出和校准缓冲区的输出，并生成二进制数。基于逐次逼近方法，数字校准块找到用于ADC偏移和非线性补偿的校正电压。通过采用ADC校准装置，可以校准每个参考电压，并且可以使用相应的校正电压来修改ADC过程中的参考电压。

2. 发明申请

US20120212359A1 ADC Calibration Apparatus 有权
标题翻译： ADC校准装置
公开(公告)号：US20120212359A1
公开(公告)日：2012-08-23
申请号：US13029754
申请日：2011-02-17
申请人： Fang-Shi Jordan Lai , Chin-Hao Chang , Manoj M. Mhala , Hsu-Feng Hsueh , Yung-Fu Lin , Cheng Yen Weng
发明人： Fang-Shi Jordan Lai , Chin-Hao Chang , Manoj M. Mhala , Hsu-Feng Hsueh , Yung-Fu Lin , Cheng Yen Weng
IPC分类号： H03M1/10 , H03K5/22
CPC分类号： H03M1/1061 , H03M1/361
摘要： An analog-to-digital (ADC) calibration apparatus comprises a calibration buffer, a comparator and a digital calibration block. Each reference voltage is sent to a track-and-hold amplifier as well as the calibration buffer. The comparator compares the output from the track-and-hold amplifier and the output from the calibration buffer and generates a binary number. Based upon a successive approximation method, the digital calibration block finds a correction voltage for ADC offset and nonlinearity compensation. By employing the ADC calibration apparatus, each reference voltage can be calibrated and the corresponding correction voltage can be used to modify the reference voltage during an ADC process.
摘要翻译：模数（ADC）校准装置包括校准缓冲器，比较器和数字校准块。每个参考电压被发送到跟踪和保持放大器以及校准缓冲器。比较器比较跟踪和保持放大器的输出和校准缓冲区的输出，并生成二进制数。基于逐次逼近方法，数字校准块找到用于ADC偏移和非线性补偿的校正电压。通过采用ADC校准装置，可以校准每个参考电压，并且可以使用相应的校正电压来修改ADC过程中的参考电压。

3. 发明授权

US08228221B2 Method and apparatus for calibrating sigma-delta modulator 有权
标题翻译：用于校准Σ-Δ调制器的方法和装置
公开(公告)号：US08228221B2
公开(公告)日：2012-07-24
申请号：US12891952
申请日：2010-09-28
申请人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin , Manoj M. Mhala , Tao Wen Chung , Chin-Hao Chang
发明人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin , Manoj M. Mhala , Tao Wen Chung , Chin-Hao Chang
IPC分类号： H03M3/02
CPC分类号： H03M3/38 , H03M3/414
摘要： In a method of converting an analog signal to digital format, an analog input signal is received and processed using sigma-delta modulation to provide a first digital signal that represents the analog input signal in digital format and to provide a second digital signal that represents a first error introduced during the sigma-delta modulation. A second error that is error introduced during the sigma-delta modulation is estimated. A pre-correction signal is determined based on the first and second digital signals. A difference between the estimated second error and the pre-correction digital signal is determined to provide a digital output signal representing the analog input signal in digital format. An error correction element operable to adjust the digital output signal based on the analog input signal, the digital output signal, and the second digital signal is controlled.
摘要翻译：在将模拟信号转换为数字格式的方法中，使用Σ-Δ调制接收和处理模拟输入信号，以提供表示数字格式的模拟输入信号的第一数字信号，并提供表示第在Σ-Δ调制期间引入的第一个误差。估计在Σ-Δ调制期间引入误差的第二个误差。基于第一和第二数字信号确定预校正信号。确定估计的第二误差和预校正数字信号之间的差异以提供表示数字格式的模拟输入信号的数字输出信号。控制基于模拟输入信号，数字输出信号和第二数字信号来调整数字输出信号的纠错元件。

4. 发明申请

US20120075132A1 METHOD AND APPARATUS FOR CALIBRATING SIGMA-DELTA MODULATOR 有权
标题翻译：用于校准SIGMA-DELTA调制器的方法和装置
公开(公告)号：US20120075132A1
公开(公告)日：2012-03-29
申请号：US12891952
申请日：2010-09-28
申请人： Fang-Shi Jordan LAI , Hsu-Feng HSUEH , Cheng Yen WENG , Yung-Fu LIN , Manoj M. MHALA , Tao Wen CHUNG , Chin-Hao CHANG
发明人： Fang-Shi Jordan LAI , Hsu-Feng HSUEH , Cheng Yen WENG , Yung-Fu LIN , Manoj M. MHALA , Tao Wen CHUNG , Chin-Hao CHANG
IPC分类号： H03M3/02
CPC分类号： H03M3/38 , H03M3/414
摘要： In a method of converting an analog signal to digital format, an analog input signal is received and processed using sigma-delta modulation to provide a first digital signal that represents the analog input signal in digital format and to provide a second digital signal that represents a first error introduced during the sigma-delta modulation. A second error that is error introduced during the sigma-delta modulation is estimated. A pre-correction signal is determined based on the first and second digital signals. A difference between the estimated second error and the pre-correction digital signal is determined to provide a digital output signal representing the analog input signal in digital format. An error correction element operable to adjust the digital output signal based on the analog input signal, the digital output signal, and the second digital signal is controlled.
摘要翻译：在将模拟信号转换为数字格式的方法中，使用Σ-Δ调制接收和处理模拟输入信号，以提供表示数字格式的模拟输入信号的第一数字信号，并提供表示第在Σ-Δ调制期间引入的第一个误差。估计在Σ-Δ调制期间引入误差的第二个误差。基于第一和第二数字信号确定预校正信号。确定估计的第二误差和预校正数字信号之间的差异以提供表示数字格式的模拟输入信号的数字输出信号。控制基于模拟输入信号，数字输出信号和第二数字信号来调整数字输出信号的纠错元件。

5. 发明授权

US08441384B2 Switched-capacitor circuit with low signal degradation 有权
标题翻译：开关电容电路信号衰减低
公开(公告)号：US08441384B2
公开(公告)日：2013-05-14
申请号：US13030862
申请日：2011-02-18
申请人： Fang-Shi Lai , Manoj M. Mhala , Yung-Fu Lin , Hsu-Feng Hsueh , Chin-Hao Chang , Cheng Yen Weng
发明人： Fang-Shi Lai , Manoj M. Mhala , Yung-Fu Lin , Hsu-Feng Hsueh , Chin-Hao Chang , Cheng Yen Weng
IPC分类号： H03M3/00
CPC分类号： H03K5/24 , H03M3/352 , H03M3/45 , H03M3/452
摘要： A switched-capacitor circuit is disclosed. The switched-capacitor circuit includes a comparator having a first and second input, a first and second sampling capacitor, and a first and second switching circuitry. The first switching circuitry charges the first and second sampling capacitor with an input signal. The second switching circuitry selectively couples the first sampling capacitor with a reference voltage and selectively couples the second sampling capacitor and the first and second input of the comparator to a common voltage. The comparator performs a compare of the input signals against the reference voltage, and outputs a signal.
摘要翻译：公开了一种开关电容器电路。开关电容器电路包括具有第一和第二输入，第一和第二采样电容器以及第一和第二开关电路的比较器。第一开关电路用输入信号对第一和第二采样电容器充电。第二开关电路选择性地将第一采样电容器与参考电压耦合，并且将第二采样电容器和比较器的第一和第二输入端选择性地耦合到公共电压。比较器执行输入信号与参考电压的比较，并输出信号。

6. 发明授权

US08279102B2 Method and apparatus for analog to digital conversion 有权
标题翻译：用于模数转换的方法和装置
公开(公告)号：US08279102B2
公开(公告)日：2012-10-02
申请号：US12898261
申请日：2010-10-05
申请人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin , Manoj M. Mhala , Tao Wen Chung , Chin-Hao Chang
发明人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin , Manoj M. Mhala , Tao Wen Chung , Chin-Hao Chang
IPC分类号： H03M1/38
CPC分类号： H03M1/1215 , H03M1/164 , H03M1/442
摘要： An analog to digital converter (ADC) comprises an input node having a variable analog input voltage, first and second switched capacitor circuits, an operational amplifier, and a control circuit. The first switched capacitor circuit has first and second capacitors and is coupled to the input node, and the second switched capacitor circuit has third and fourth capacitors and is coupled to the input node. The operational amplifier is configured to be conditionally coupled to only one of the first and second switched capacitor circuits at a time and configured to conditionally provide feedback to the switched capacitor circuits via an output node. The control circuit is coupled to the first and second switched capacitor circuits for conditional coupling to the operational amplifier.
摘要翻译：模数转换器（ADC）包括具有可变模拟输入电压的输入节点，第一和第二开关电容器电路，运算放大器和控制电路。第一开关电容器电路具有第一和第二电容器并且耦合到输入节点，并且第二开关电容器电路具有第三和第四电容器并且耦合到输入节点。运算放大器被配置为一次有条件地耦合到第一和第二开关电容器电路中的一个，并且被配置为通过输出节点有条件地向开关电容器电路提供反馈。控制电路耦合到第一和第二开关电容器电路以用于与运算放大器的条件耦合。

7. 发明申请

US20120081244A1 METHOD AND APPARATUS FOR ANALOG TO DIGITAL CONVERSION 有权
标题翻译：用于模拟数字转换的方法和装置
公开(公告)号：US20120081244A1
公开(公告)日：2012-04-05
申请号：US12898261
申请日：2010-10-05
申请人： Fang-Shi Jordan LAI , Hsu-Feng HSUEH , Cheng Yen WENG , Yung-Fu LIN , Manoj M. MHALA , Tao Wen CHUNG , Chin-Hao CHANG
发明人： Fang-Shi Jordan LAI , Hsu-Feng HSUEH , Cheng Yen WENG , Yung-Fu LIN , Manoj M. MHALA , Tao Wen CHUNG , Chin-Hao CHANG
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： H03M1/1215 , H03M1/164 , H03M1/442
摘要： An analog to digital converter (ADC) comprises an input node having a variable analog input voltage, first and second switched capacitor circuits, an operational amplifier, and a control circuit. The first switched capacitor circuit has first and second capacitors and is coupled to the input node, and the second switched capacitor circuit has third and fourth capacitors and is coupled to the input node. The operational amplifier is configured to be conditionally coupled to only one of the first and second switched capacitor circuits at a time and configured to conditionally provide feedback to the switched capacitor circuits via an output node. The control circuit is coupled to the first and second switched capacitor circuits for conditional coupling to the operational amplifier.
摘要翻译：模数转换器（ADC）包括具有可变模拟输入电压的输入节点，第一和第二开关电容器电路，运算放大器和控制电路。第一开关电容器电路具有第一和第二电容器并且耦合到输入节点，并且第二开关电容器电路具有第三和第四电容器并且耦合到输入节点。运算放大器被配置为一次有条件地耦合到第一和第二开关电容器电路中的一个，并且被配置为通过输出节点有条件地向开关电容器电路提供反馈。控制电路耦合到第一和第二开关电容器电路以用于与运算放大器的条件耦合。

8. 发明授权

US08692571B2 Apparatus and method for measuring degradation of CMOS VLSI elements 有权
标题翻译：用于测量CMOS VLSI元件退化的装置和方法
公开(公告)号：US08692571B2
公开(公告)日：2014-04-08
申请号：US13183521
申请日：2011-07-15
申请人： Fang-Shi Jordan Lai , Chih-Cheng Lu , Yung-Fu Lin , Hsu-Feng Hsueh , Chin-Hao Chang , Cheng Yen Weng , Manoj M. Mhala
发明人： Fang-Shi Jordan Lai , Chih-Cheng Lu , Yung-Fu Lin , Hsu-Feng Hsueh , Chin-Hao Chang , Cheng Yen Weng , Manoj M. Mhala
IPC分类号： G01R31/00 , G01R31/319
CPC分类号： G01R31/31924 , G01R31/2642
摘要： The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages.
摘要翻译：集成电路的可靠性是根据样品金属氧化物半导体（MOS）器件的可操作特性推断的，该器件可以切换地耦合到漏极/源极偏置和栅极输入电压，这些标称电压和电流条件会提高应力并引起临时或永久性降解，例如热载流子注入（HCI），偏置温度不稳定性（BTI，NBTI，PBTI），时间依赖介电击穿（TDDB）。所测试的MOS器件（优选同时或同时测试的PMOS和NMOS器件）被配置为向具有级联的反相器级的环形振荡器供电的电流源，从而改变振荡器频率作为应力的影响的量度在被测设备上，但不会升高施加到逆变器级的应力。

9. 发明授权

US08493259B2 Pipeline analog-to-digital converter 有权
标题翻译：管道模数转换器
公开(公告)号：US08493259B2
公开(公告)日：2013-07-23
申请号：US13311639
申请日：2011-12-06
申请人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Chin-Hao Chang , Cheng Yen Weng , Chih-Cheng Lu , Manoj M. Mhala , Yung-Fu Lin
发明人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Chin-Hao Chang , Cheng Yen Weng , Chih-Cheng Lu , Manoj M. Mhala , Yung-Fu Lin
IPC分类号： H03M1/34
CPC分类号： H03M1/1014 , H03M1/0695 , H03M1/168 , H03M1/44
摘要： A pipelined ADC includes a first, second, and third pairs of comparators. The first pair of comparators compare an input voltage to a first positive reference voltage and to a first negative reference voltage. The second pair of comparators compare the input voltage to a second positive reference voltage and to a second negative reference voltage. Each comparator of the first and second pairs of comparators outputs a digital signal to an encoder. A third pair of comparators compares the input voltage to a third positive reference voltage and to a third negative reference voltage, and a comparator compares the input voltage to ground. The comparator and each comparator of the third pair of comparators is configured to output respective digital signals to an encoder. A multiplying digital-to-analog converter outputs a voltage based on the input voltage, an output from the encoder, and an output of the random number generator.
摘要翻译：流水线模数转换器包括第一，第二和第三对比较器。第一对比较器将输入电压与第一正参考电压和第一负参考电压进行比较。第二对比较器将输入电压与第二正参考电压和第二负参考电压进行比较。第一和第二对比较器的每个比较器向编码器输出数字信号。第三对比较器将输入电压与第三正参考电压和第三负参考电压进行比较，比较器将输入电压与地比较。比较器和第三对比较器对的每个比较器被配置为将相应的数字信号输出到编码器。乘法数模转换器输出基于输入电压的电压，来自编码器的输出和随机数发生器的输出。

10. 发明申请

US20130141260A1 PIPELINE ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：管道模拟数字转换器
公开(公告)号：US20130141260A1
公开(公告)日：2013-06-06
申请号：US13311639
申请日：2011-12-06
申请人： Fang-Shi Jordan LAI , Hsu-Feng HSUEH , Chin-Hao CHANG , Cheng Yen WENG , Chih-Cheng LU , Manoj M. MHALA , Yung-Fu LIN
发明人： Fang-Shi Jordan LAI , Hsu-Feng HSUEH , Chin-Hao CHANG , Cheng Yen WENG , Chih-Cheng LU , Manoj M. MHALA , Yung-Fu LIN
IPC分类号： H03M1/12 , H03M1/34
CPC分类号： H03M1/1014 , H03M1/0695 , H03M1/168 , H03M1/44
摘要： A pipelined ADC includes a first, second, and third pairs of comparators. The first pair of comparators compare an input voltage to a first positive reference voltage and to a first negative reference voltage. The second pair of comparators compare the input voltage to a second positive reference voltage and to a second negative reference voltage. Each comparator of the first and second pairs of comparators outputs a digital signal to an encoder. A third pair of comparators compares the input voltage to a third positive reference voltage and to a third negative reference voltage, and a comparator compares the input voltage to ground. The comparator and each comparator of the third pair of comparators is configured to output respective digital signals to an encoder. A multiplying digital-to-analog converter outputs a voltage based on the input voltage, an output from the encoder, and an output of the random number generator.
摘要翻译：流水线模数转换器包括第一，第二和第三对比较器。第一对比较器将输入电压与第一正参考电压和第一负参考电压进行比较。第二对比较器将输入电压与第二正参考电压和第二负参考电压进行比较。第一和第二对比较器的每个比较器向编码器输出数字信号。第三对比较器将输入电压与第三正参考电压和第三负参考电压进行比较，比较器将输入电压与地比较。比较器和第三对比较器对的每个比较器被配置为将相应的数字信号输出到编码器。乘法数模转换器输出基于输入电压的电压，来自编码器的输出和随机数发生器的输出。

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