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    • 22. 发明申请
    • A/D CONVERTER
    • A / D转换器
    • US20100007541A1
    • 2010-01-14
    • US12439444
    • 2007-08-10
    • Masakazu ShigemoriKoji SushiharaKenji Murata
    • Masakazu ShigemoriKoji SushiharaKenji Murata
    • H03M1/34
    • H03M1/0624H03M1/206H03M1/365
    • The conventional A/D converter has a drawback that the conversion precision is degraded when the operation periods of the constituents of the A/D converter are shortened due to the duty ratio of an external input clock because the operation periods of the constituents of the A/D converter depend on the pulse width of the external input clock. However, a highly-precise A/D conversion operation independent of the duty ratio of the external input clock can be realized by providing a circuit for detecting the operation periods of the constituents of the A/D converter, and adjusting the duty ratio of the operation clock according to the detected operation periods of the constituents of the A/D converter.
    • 传统的A / D转换器具有这样的缺点,即当A / D转换器的构成要素的操作周期由于外部输入时钟的占空比而缩短时,转换精度降低,因为A / D转换器取决于外部输入时钟的脉冲宽度。 然而,与外部输入时钟的占空比无关的高精度A / D转换操作可以通过提供用于检测A / D转换器的构成要素的操作周期的电路来实现,并且调整占空比 根据检测到的A / D转换器的构成要素的运行时间来设定运转时钟。
    • 24. 发明授权
    • A/D converter for performing pipeline processing
    • 用于执行流水线处理的A / D转换器
    • US06700524B2
    • 2004-03-02
    • US10256238
    • 2002-09-27
    • Junichi NakaYoichi OkamotoYoshitsugu InagakiKenji MurataKoji Oka
    • Junichi NakaYoichi OkamotoYoshitsugu InagakiKenji MurataKoji Oka
    • H03M138
    • H03M1/007H03M1/0695H03M1/44
    • An A/D converter comprises a pipeline stage array in which plural pipeline stages are connected in series, each pipeline stage performing a pipeline operation on an inputted analog voltage to output a digital voltage; a number-of-bits control circuit for outputting a number-of-bits selection signal which indicates whether the operation of each pipeline stage should be carried out or halted, according to a number-of-bits control signal which indicates a resolution; and a correction circuit for compensating a digital value to be output, according to the number-of-bits control signal. Therefore, when resolution of the A/D converter, which is requested by the system, is changed, only the pipeline stages required for realizing the requested resolution are operated while the other pipeline stages are halted, whereby a reduction in power consumption of the A/D converter is realized and, simultaneously, a breakdown of an output from the A/D converter is avoided.
    • A / D转换器包括一个其中多个流水线级串联连接的流水线阵列,每个流水线级对所输入的模拟电压进行流水线操作以输出数字电压; 根据指示分辨率的位数控制信号,输出指示每个流水线级的操作是否应被执行或停止的位数选择信号的位数控制电路; 以及根据位数控制信号补偿要输出的数字值的校正电路。 因此,当系统请求的A / D转换器的分辨率改变时,仅在实现所请求的分辨率所需的流水线阶段在其它流水线级停止的同时被操作,从而降低了A / D转换器,同时避免了A / D转换器的输出故障。
    • 25. 发明授权
    • Latch circuit for amplifying an analog signal and converting an analog
signal into a digital signal
    • 用于放大模拟信号并将模拟信号转换为数字信号的锁存电路
    • US5719513A
    • 1998-02-17
    • US699808
    • 1996-08-20
    • Keiichi KusumotoKenji MurataAkira Matsuzawa
    • Keiichi KusumotoKenji MurataAkira Matsuzawa
    • H03K3/012H03K3/037
    • H03K3/037H03K3/012
    • The present invention discloses an improved latch circuit. In the latch circuit, a composite gate takes in a basic clock signal and a delayed clock signal which is delayed by a delay circuit for a specific amount with respect to the basic clock signal, and puts out to a second drive circuit a first signal identical in waveform with the basic block signal, and further puts out to a first drive circuit a second signal that is delayed in the rising timing with respect to the first signal. As a result of such arrangement, when a transition is made from a feedback period during which an input switch has an off state while a feedback switch has an on state to a sampling period during which the input switch has an on state while the feedback switch has an off state, neither the input switch nor the feedback switch has an on state.
    • 本发明公开了一种改进的锁存电路。 在锁存电路中,复合栅极接收基本时钟信号和相对于基本时钟信号延迟特定量的延迟电路的延迟时钟信号,并向第二驱动电路输出相同的第一信号 具有基本块信号的波形,并且进一步向第一驱动电路输出相对于第一信号在上升定时中延迟的第二信号。 作为这种布置的结果,当反馈开关具有断开状态的反馈周期转变到反馈开关具有接通状态到输入开关处于导通状态的采样周期,而反馈开关 具有断开状态,输入开关和反馈开关都不具有导通状态。
    • 29. 发明授权
    • Vehicle door frame structure
    • 车门框架结构
    • US08458959B2
    • 2013-06-11
    • US12593645
    • 2008-03-28
    • Yasuhiro OhtakeKenji MurataShigenobu OhsawaJiro Yoshihara
    • Yasuhiro OhtakeKenji MurataShigenobu OhsawaJiro Yoshihara
    • B60J5/04
    • B60J5/0402B60J10/21B60J10/86B60J10/88
    • A vehicle door frame structure has an upper sash member located along a roof panel of a vehicle body and also has a vertical pillar sash member located along a center pillar of the vehicle body. The upper sash member has, at its linear end joined to the vertical pillar sash member side, an aesthetically designed section and an inner frame portion. The aesthetically designed section is located on the outer side of the door, and the inner frame portion is located closer to the vehicle interior than the aesthetically designed section and is shorter in length than the aesthetically designed section. The vertical pillar sash member has at its upper end a superposed contact section that is superposed, in the direction of the thickness of the door, on an end of the inner frame portion of the upper sash member, and the superposed contact section and the inner frame portion are joined together while being superposed on each other.
    • 车门框架结构具有沿着车身的车顶板定位的上框架构件,并且还具有沿着车身的中心柱定位的立柱框架构件。 上框架构件在其直线端部处连接到垂直支撑框架构件侧,具有美观设计的部分和内框架部分。 美观设计的部分位于门的外侧,并且内框架部分位于比美观设计的部分更靠近车辆内部并且比美观设计的部分的长度更短。 立柱框架构件的上端具有重叠的接触部分,其在门的厚度方向上重叠在上框架构件的内框架部分的端部上,并且叠置的接触部分和内部 框架部分彼此叠合在一起。