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21. 发明申请

US20120190133A1 THROUGH SILICON VIA REPAIR 失效
标题翻译：通过修复的硅
公开(公告)号：US20120190133A1
公开(公告)日：2012-07-26
申请号：US13013378
申请日：2011-01-25
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L21/66 , B23P19/00 , H01L21/50
CPC分类号： H01L22/30 , H01L21/76886 , H01L21/76898 , H01L22/14 , H01L22/20 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , Y10T29/5313 , Y10T29/532 , H01L2924/00
摘要： Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.
摘要翻译：用于改变布线路径的电阻的方法和系统。将布线路径的电阻与目标电阻值进行比较。如果布线路径的电阻超过目标电阻值，则选择性地向布线路径施加电流，以物理地改变布线路径的一部分。可以选择电流来改变布线路径，使得电阻下降到小于或等于目标电阻值的值。

22. 发明申请

US20090225481A1 E-Fuse Used to Disable a Triggering Network 失效
标题翻译：电子保险丝用于禁用触发网络
公开(公告)号：US20090225481A1
公开(公告)日：2009-09-10
申请号：US12041962
申请日：2008-03-04
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H9/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A device and/or circuit having an e-fuse is provided to disable a triggering network, and more specifically, an e-fuse is used to disable an electrostatic discharge (ESD) RC triggering network after device installation. The device and/or circuit includes a triggering network electrically coupled to an electrostatic discharge (ESD) protection device. An e-fuse is electrically coupled with the triggering network and configured to render the ESD protection device insensitive to a triggering signal after blowing the e-fuse.
摘要翻译：提供具有电子保险丝的装置和/或电路以禁用触发网络，更具体地，使用电子熔丝来在设备安装之后禁用静电放电（ESD）RC触发网络。该装置和/或电路包括电耦合到静电放电（ESD）保护装置的触发网络。电子熔丝与触发网络电耦合并且被配置为使得ESD保护装置在吹动电熔丝之后对触发信号不敏感。

23. 发明申请

US20090179268A1 DESIGN STRUCTURES FOR HIGH-VOLTAGE INTEGRATED CIRCUITS 失效
标题翻译：高压集成电路的设计结构
公开(公告)号：US20090179268A1
公开(公告)日：2009-07-16
申请号：US12059034
申请日：2008-03-31
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Souvick Mitra
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Souvick Mitra
IPC分类号： H01L29/786 , G06F17/50
CPC分类号： H01L27/1203
摘要： Design structures for high-voltage integrated circuits. The design structure, which is formed using a semiconductor-on-insulator (SOI) substrate, may include device structure with a semiconductor body positioned between first and second gate electrodes. The first and second gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the first and second gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrently with a process forming other device isolation regions.
摘要翻译：高压集成电路的设计结构。使用绝缘体上半导体（SOI）衬底形成的设计结构可以包括具有位于第一和第二栅电极之间的半导体本体的器件结构。第一和第二栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。电介质层将第一和第二栅极电极与半导体本体分开。这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，介电材料可与形成其它器件隔离区的工艺同时进行。

24. 发明申请

US20090179267A1 SEMICONDUCTOR-ON-INSULATOR HIGH-VOLTAGE DEVICE STRUCTURES, METHODS OF FABRICATING SUCH DEVICE STRUCTURES, AND DESIGN STRUCTURES FOR HIGH-VOLTAGE CIRCUITS 失效
标题翻译：半导体绝缘体高压器件结构，制造这种器件结构的方法以及高压电路的设计结构
公开(公告)号：US20090179267A1
公开(公告)日：2009-07-16
申请号：US12013101
申请日：2008-01-11
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Mitra Souvick
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Mitra Souvick
IPC分类号： H01L27/12 , H01L21/786
CPC分类号： H01L27/1203 , H01L21/84
摘要： High-voltage device structures, methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes, and design structures for high-voltage circuits. The planar device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a semiconductor body positioned between two gate electrodes. The gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrent with a process forming device isolation regions.
摘要翻译：高电压器件结构，使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法，以及高压电路的设计结构。使用绝缘体上半导体（SOI）衬底形成的平面器件结构包括位于两个栅电极之间的半导体本体。栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。电介质层将每个栅电极与半导体本体分开。这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，其可以与形成器件隔离区的工艺同时发生。

25. 发明授权

US07772651B2 Semiconductor-on-insulator high-voltage device structures, methods of fabricating such device structures, and design structures for high-voltage circuits 失效
标题翻译：绝缘体上半导体高压器件结构，制造这种器件结构的方法，以及高压电路的设计结构
公开(公告)号：US07772651B2
公开(公告)日：2010-08-10
申请号：US12013101
申请日：2008-01-11
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Mitra Souvick
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Mitra Souvick
IPC分类号： H01L29/78
CPC分类号： H01L27/1203 , H01L21/84
摘要： High-voltage device structures, methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes, and design structures for high-voltage circuits. The planar device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a semiconductor body positioned between two gate electrodes. The gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrent with a process forming device isolation regions.
摘要翻译：高电压器件结构，使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法，以及高压电路的设计结构。使用绝缘体上半导体（SOI）衬底形成的平面器件结构包括位于两个栅电极之间的半导体本体。栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。电介质层将每个栅电极与半导体本体分开。这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，其可以与形成器件隔离区的工艺同时发生。

26. 发明授权

US08610249B2 Non-planar capacitor and method of forming the non-planar capacitor 有权
标题翻译：非平面电容器和非平面电容器的形成方法
公开(公告)号：US08610249B2
公开(公告)日：2013-12-17
申请号：US13434964
申请日：2012-03-30
申请人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L21/02
CPC分类号： H01L27/0805 , H01L21/845 , H01L27/1211 , H01L28/90 , H01L29/94
摘要： Disclosed herein are embodiments of non-planar capacitor. The non-planar capacitor can comprise a plurality of fins above a semiconductor substrate. Each fin can comprise at least an insulator section on the semiconductor substrate and a semiconductor section, which has essentially uniform conductivity, stacked above the insulator section. A gate structure can traverse the center portions of the fins. This gate structure can comprise a conformal dielectric layer and a conductor layer (e.g., a blanket or conformal conductor layer) on the dielectric layer. Such a non-planar capacitor can exhibit a first capacitance, which is optionally tunable, between the conductor layer and the fins and a second capacitance between the conductor layer and the semiconductor substrate. Also disclosed herein are method embodiments, which can be used to form such a non-planar capacitor and which are compatible with current state of the art multi-gate non-planar field effect transistor (MUGFET) processing.
摘要翻译：这里公开了非平面电容器的实施例。非平面电容器可以包括在半导体衬底上方的多个鳍片。每个翅片可以包括半导体衬底上的至少绝缘体部分和在绝缘体部分上方堆叠具有基本上均匀的导电性的半导体部分。门结构可以穿过翅片的中心部分。该栅极结构可以包括在电介质层上的共形介电层和导体层（例如，覆盖层或保形导体层）。这种非平面电容器可以在导体层和散热片之间展现可选地可调谐的第一电容和导体层与半导体衬底之间的第二电容。本文还公开了可用于形成这种非平面电容器并且与现有技术的多栅极非平面场效应晶体管（MUGFET）处理兼容的方法实施例。

27. 发明授权

US08575718B2 Programmable electrical fuse 失效
标题翻译：可编程电气保险丝
公开(公告)号：US08575718B2
公开(公告)日：2013-11-05
申请号：US13289529
申请日：2011-11-04
申请人： Michael J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
发明人： Michael J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
IPC分类号： H01L23/52 , H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.
摘要翻译：本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

28. 发明申请

US20130256835A1 NON-PLANAR CAPACITOR AND METHOD OF FORMING THE NON-PLANAR CAPACITOR 有权
标题翻译：非平面电容器和形成非平面电容器的方法
公开(公告)号：US20130256835A1
公开(公告)日：2013-10-03
申请号：US13434964
申请日：2012-03-30
申请人： James P. Di Sarro , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： James P. Di Sarro , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L27/0805 , H01L21/845 , H01L27/1211 , H01L28/90 , H01L29/94
摘要： Disclosed herein are embodiments of non-planar capacitor. The non-planar capacitor can comprise a plurality of fins above a semiconductor substrate. Each fin can comprise at least an insulator section on the semiconductor substrate and a semiconductor section, which has essentially uniform conductivity, stacked above the insulator section. A gate structure can traverse the center portions of the fins. This gate structure can comprise a conformal dielectric layer and a conductor layer (e.g., a blanket or conformal conductor layer) on the dielectric layer. Such a non-planar capacitor can exhibit a first capacitance, which is optionally tunable, between the conductor layer and the fins and a second capacitance between the conductor layer and the semiconductor substrate. Also disclosed herein are method embodiments, which can be used to form such a non-planar capacitor and which are compatible with current state of the art multi-gate non-planar field effect transistor (MUGFET) processing.
摘要翻译：这里公开了非平面电容器的实施例。非平面电容器可以包括在半导体衬底上方的多个鳍片。每个翅片可以包括半导体衬底上的至少绝缘体部分和在绝缘体部分上方堆叠具有基本上均匀的导电性的半导体部分。门结构可以穿过翅片的中心部分。该栅极结构可以包括在电介质层上的共形介电层和导体层（例如，覆盖层或保形导体层）。这种非平面电容器可以在导体层和散热片之间展现可选地可调谐的第一电容和导体层与半导体衬底之间的第二电容。本文还公开了可用于形成这种非平面电容器并且与现有技术的多栅极非平面场效应晶体管（MUGFET）处理兼容的方法实施例。

29. 发明申请

US20120049321A1 PROGRAMMABLE ELECTRICAL FUSE 失效
标题翻译：可编程电气保险丝
公开(公告)号：US20120049321A1
公开(公告)日：2012-03-01
申请号：US13289529
申请日：2011-11-04
申请人： Michael J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
发明人： Michael J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
IPC分类号： H01L23/525 , H01L21/326
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.
摘要翻译：本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

30. 发明申请

US20080145958A1 MONITORING OF ELECTROSTATIC DISCHARGE (ESD) EVENTS DURING SEMICONDUCTOR MANUFACTURE USING ESD SENSITIVE RESISTORS 审中-公开
标题翻译：使用ESD敏感电阻监测半导体制造过程中的静电放电（ESD）事件
公开(公告)号：US20080145958A1
公开(公告)日：2008-06-19
申请号：US11611258
申请日：2006-12-15
申请人： Michel J. Abou-Khalil , Robert J. Gauthier , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher Stephen Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher Stephen Putnam
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L22/14 , H01L22/20 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A monitor semiconductor chip that incorporates ESD sensitive resistors is subjected to the same steps in a semiconductor manufacturing process to which functional semiconductor chips are subjected. The ESD sensitive resistors are configured to experience non-volatile changes in resistance in response to ESD events, such that the resistors retain the changes in resistance after dissipation of the ESD events have occurred. As a result, the occurrence of an ESD event, and in some instances, the magnitude of an ESD event, can be detected by monitoring the resistance of the ESD sensitive resistors after one or more steps in a semiconductor manufacturing process.
摘要翻译：在ESD功能半导体芯片受到的半导体制造工序中，具有ESD敏感电阻的监视器半导体芯片进行相同的工序。 ESD敏感电阻被配置为响应于ESD事件而经历电阻的非易失性变化，使得电阻器在ESD事件消散之后保持电阻的变化。结果，通过在半导体制造过程中的一个或多个步骤之后监视ESD敏感电阻器的电阻，可以检测到ESD事件的发生，并且在一些情况下，ESD事件的幅度。

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