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21. 发明授权

US07582929B2 Electronic device including discontinuous storage elements 有权
标题翻译：电子设备包括不连续的存储元件
公开(公告)号：US07582929B2
公开(公告)日：2009-09-01
申请号：US11188999
申请日：2005-07-25
申请人： Michael A. Sadd , Ko-Min Chang , Gowrishankar L. Chindalore , Cheong M. Hong , Craig T. Swift
发明人： Michael A. Sadd , Ko-Min Chang , Gowrishankar L. Chindalore , Cheong M. Hong , Craig T. Swift
IPC分类号： H01L29/94
CPC分类号： H01L29/7887 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825
摘要： An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a portion of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein at least one discontinuous storage element lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and a primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface of the substrate. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.
摘要翻译：电子设备可以包括位于沟槽内的不连续存储元件。在一个实施例中，电子设备可以包括具有包括壁和底部的沟槽的衬底。电子设备还可以包括位于沟槽内的不连续存储元件的一部分。电子器件还可以包括第一栅电极，其中至少一个不连续存储元件沿着沟槽的壁位于第一栅电极的上表面和衬底的主表面之间的高度处。电子器件还可以包括覆盖在第一栅电极和衬底的主表面上的第二栅电极。在另一个实施例中，导线可以电连接到一个或多个存储单元的行或列，而另一个导线可以是更多行或更多列的存储单元。

22. 发明授权

US07524719B2 Method of making self-aligned split gate memory cell 失效
标题翻译：制造自对准分离栅极存储单元的方法
公开(公告)号：US07524719B2
公开(公告)日：2009-04-28
申请号：US11469163
申请日：2006-08-31
申请人： Robert F. Steimle , Ko-Min Chang
发明人： Robert F. Steimle , Ko-Min Chang
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A method for forming a split gate memory cell (10,11) using a semiconductor substrate (12) includes forming a select gate structure (48) and a sacrificial structure (50) over the substrate. An opening is between the select gate structure and the sacrificial structure. The opening is lined with a storage layer (56,168). The opening is further filled with select gate material (58,170). The sacrificial structure is removed after filling the opening with the select gate material.
摘要翻译：使用半导体衬底（12）形成分离栅极存储单元（10,11）的方法包括在衬底上形成选择栅极结构（48）和牺牲结构（50）。选择栅极结构和牺牲结构之间有一个开口。开口衬有存储层（56,168）。开口进一步填充选择栅极材料（58,170）。在用选择栅极材料填充开口之后去除牺牲结构。

23. 发明申请

US20080188052A1 Split-gate thin film storage NVM cell with reduced load-up/trap-up effects 有权
标题翻译：分流栅薄膜存储NVM单元，具有降低的加载/陷阱效应
公开(公告)号：US20080188052A1
公开(公告)日：2008-08-07
申请号：US11671809
申请日：2007-02-06
申请人： Brian A. Winstead , Taras A. Kirichenko , Konstantin V. Loiko , Ramachandran Muralidhar , Rajesh A. Rao , Sung-Taeg Kang , Ko-Min Chang , Jane Yater
发明人： Brian A. Winstead , Taras A. Kirichenko , Konstantin V. Loiko , Ramachandran Muralidhar , Rajesh A. Rao , Sung-Taeg Kang , Ko-Min Chang , Jane Yater
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , H01L21/28273 , H01L29/42328 , H01L29/66825 , H01L29/7885
摘要： A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device (10) by forming a select gate structure (3) on a first dielectric layer (2) over a substrate (1); forming a control gate structure (6) on a second dielectric layer (5) having embedded nanocrystals (15, 16) so that the control gate (6) is adjacent to the select gate structure (3) but separated therefrom by a gap (8); forming a floating doped region (4) in the substrate (1) below the gap (8) formed between the select gate structure and control gate structure; and forming source/drain regions (11, 12) in the substrate to define a channel region that includes the floating doped region (4).
摘要翻译：公开了一种半导体工艺和装置，用于通过在衬底（1）上的第一介电层（2）上形成选择栅极结构（3）来形成分裂栅极薄膜存储NVM器件（10）。在具有嵌入的纳米晶体（15,16）的第二介电层（5）上形成控制栅极结构（6），使得所述控制栅极（6）与所述选择栅极结构（3）相邻，但是通过间隙（8 ）; 在形成在选择栅极结构和控制栅极结构之间的间隙（8）下面的衬底（1）中形成浮置掺杂区（4）; 以及在所述衬底中形成源/漏区（11,12）以限定包括所述浮置掺杂区（4）的沟道区。

24. 发明授权

US06939767B2 Multi-bit non-volatile integrated circuit memory and method therefor 失效
标题翻译：多位非易失性集成电路存储器及其方法
公开(公告)号：US06939767B2
公开(公告)日：2005-09-06
申请号：US10716956
申请日：2003-11-19
申请人： Alexander B. Hoefler , Ko-Min Chang
发明人： Alexander B. Hoefler , Ko-Min Chang
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , B82Y10/00 , H01L27/115 , H01L29/42332 , H01L29/7887
摘要： A non-volatile memory (10) includes at least two buried bit lines (45, 47) formed within a semiconductor substrate (12), a charge storage layer (18) overlying the semiconductor substrate (12); a control gate (26) overlying the charge storage layer (18); an insulating liner (30) overlying the control gate; and first and second conductive sidewall spacer control gates (32, 34). Multiple programmable charge storage regions (42) and (41, 44) are created within the charge storage layer (18) beneath respective ones of the control gate (26) and the first and second sidewall spacer control gates (32, 34). Also, the non-volatile memory (10) is a virtual ground NOR type multi-bit flash EEPROM (electrically erasable programmable read only memory). By using conductive sidewall spacers as the control gates, a very dense multi-bit non-volatile memory can be manufactured.
摘要翻译：非易失性存储器（10）包括形成在半导体衬底（12）内的至少两个掩埋位线（45,47），覆盖半导体衬底（12）的电荷存储层（18）; 覆盖电荷存储层（18）的控制栅极（26）; 覆盖所述控制门的绝缘衬垫（30）; 以及第一和第二导电侧壁间隔物控制门（32,34）。在电荷存储层（18）内，在控制栅极（26）和第一和第二侧壁间隔物控制栅极（32,34）的相应一个之下产生多个可编程电荷存储区域（42）和（41,44）。此外，非易失性存储器（10）是虚拟NOR型多位闪存EEPROM（电可擦除可编程只读存储器）。通过使用导电侧壁间隔件作为控制栅极，可以制造非常密集的多位非易失性存储器。

25. 发明授权

US5474947A Nonvolatile memory process 失效
标题翻译：非易失性存储过程
公开(公告)号：US5474947A
公开(公告)日：1995-12-12
申请号：US172984
申请日：1993-12-27
申请人： Ko-Min Chang , Bruce L. Morton , Henry Y. Choe , Clinton C. K. Kuo
发明人： Ko-Min Chang , Bruce L. Morton , Henry Y. Choe , Clinton C. K. Kuo
IPC分类号： H01L21/8247
CPC分类号： H01L27/11517
摘要： A process for fabricating an improved nonvolatile memory device includes the formation of a control gate electrode (70) which overlies a floating gate electrode (42) and is separated therefrom by an inter-level-dielectric layer (62). The control gate electrode (70) and the underlying floating gate electrode (42) form a stacked gate structure (72) located in the active region (44) of a semiconductor substrate (40). An electrically insulating sidewall spacer (54) is formed at the edges of the floating gate electrode (42) and electrically isolates the control gate (70) from the semiconductor substrate (40). During the fabrication process, implanted memory regions (56, 58) are formed in the active region (44) prior to the formation of control gate electrode (70). A word-line (68) and the control gate (70) are formed by anisotropic etching of a semiconductor layer (66), which is deposited to overlie inter-level-dielectric layer (62). During the etching process, inter-level-dielectric layer (62) prevents the removal of surface portions of semiconductor substrate (40).
摘要翻译：一种用于制造改进的非易失性存储器件的方法包括形成覆盖在浮栅电极（42）上的控制栅电极（70），并通过层间电介质层（62）与其分开。控制栅电极（70）和底层浮栅电极（42）形成位于半导体衬底（40）的有源区（44）中的层叠栅结构（72）。在浮栅电极（42）的边缘处形成电绝缘的侧壁间隔物（54），并将控制栅极（70）与半导体衬底（40）电隔离。在制造过程中，在形成控制栅电极（70）之前，在有源区（44）中形成植入的存储区（56,58）。通过各向异性蚀刻形成字线（68）和控制栅极（70），半导体层（66）沉积到层间电介质层（62）上。在蚀刻过程中，层间电介质层（62）防止去除半导体衬底（40）的表面部分。

26. 发明授权

US5422846A Nonvolatile memory having overerase protection 失效
标题翻译：非易失性存储器具有过度保护
公开(公告)号：US5422846A
公开(公告)日：1995-06-06
申请号：US222066
申请日：1994-04-04
申请人： Kuo-Tung Chang , Bruce L. Morton , Ko-Min Chang
发明人： Kuo-Tung Chang , Bruce L. Morton , Ko-Min Chang
IPC分类号： G11C16/16 , G11C11/40
CPC分类号： G11C16/16
摘要： A nonvolatile memory (20) includes an array of floating gate transistors (22) organized as rows and columns. Word lines of adjacent rows are coupled together to form shared word lines. In one embodiment, a coupling transistor (56-61) is used to couple the sources of the floating gate transistors (36, 39-55) of a row to a predetermined potential in response to the shared word line being selected. The sources of the unselected floating gate transistors of the array (22) are isolated. In another embodiment, an inverter (113, 114, and 115) couples the sources to zero volts in response to the shared word line being selected. The conductivity of the floating gate transistors (36, 39-55) is controlled in response to the logic state of the shared word lines to ensure that unselected cells do not adversely affect the operation of the nonvolatile memory.
摘要翻译：非易失性存储器（20）包括以行和列组织的浮栅晶体管阵列（22）。相邻行的字线被耦合在一起以形成共享字线。在一个实施例中，耦合晶体管（56-61）用于响应于所选择的共享字线将行的浮置栅晶体管（36,39-55）的源耦合到预定电位。阵列（22）的未选择的浮栅晶体管的源极被隔离。在另一个实施例中，响应于所选择的共享字线，反相器（113,114和115）将源耦合到零伏特。响应于共享字线的逻辑状态来控制浮栅晶体管（36,39-55）的电导率，以确保未选择的单元不会不利地影响非易失性存储器的操作。

27. 发明授权

US5357476A Apparatus and method for erasing a flash EEPROM 失效
标题翻译：擦除闪存EEPROM的装置和方法
公开(公告)号：US5357476A
公开(公告)日：1994-10-18
申请号：US69327
申请日：1993-06-01
申请人： Clinton C. K. Kuo , Ko-Min Chang , Henry Y. Choe
发明人： Clinton C. K. Kuo , Ko-Min Chang , Henry Y. Choe
IPC分类号： G11C16/16 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404
摘要： A flash EEPROM array (22) is erased and a threshold voltage distribution of the erased flash EEPROM cells (36, 39-46) is converged to within a predetermined voltage range by using a two-step erasing procedure. In the first step, flash EEPROM array (22) is electrically bulk erased using a conventional bulk erase procedure. Electrons are tunneled from the floating gate (38) to the source, causing cells (36, 39-46) to have a relatively low threshold voltage. In the second step, the threshold voltage distribution of the array (22) is converged to within the predetermined voltage range by grounding the source and drain of each cell (36, 39-46), while concurrently applying a high positive voltage to the control gate (27) of each cell (36, 39-46). Some electrons are tunneled back to the floating gate (38), thus converging the threshold voltage distribution to within a predetermined range.
摘要翻译：闪存EEPROM阵列（22）被擦除，并且擦除的快闪EEPROM单元（36,39-46）的阈值电压分布通过使用两步擦除过程而被收敛到预定电压范围内。在第一步中，使用传统的大容量擦除程序，电子体积擦除快闪EEPROM阵列（22）。电子从浮动栅极（38）隧穿到源极，导致电池（36,39-46）具有相对低的阈值电压。在第二步骤中，通过使每个单元（36,39-46）的源极和漏极接地而将阵列（22）的阈值电压分布收敛到预定电压范围内，同时向控制器施加高正电压（36,39-46）的门（27）。一些电子被隧穿回到浮动栅极（38），从而将阈值电压分布会聚到预定范围内。

28. 发明授权

US09136360B1 Methods and structures for charge storage isolation in split-gate memory arrays 有权
标题翻译：分闸存储器阵列中电荷存储隔离的方法和结构
公开(公告)号：US09136360B1
公开(公告)日：2015-09-15
申请号：US14297657
申请日：2014-06-06
申请人： Asanga H. Perera , Ko-Min Chang , Craig T. Swift
发明人： Asanga H. Perera , Ko-Min Chang , Craig T. Swift
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L29/66833 , H01L27/11521 , H01L29/42328 , H01L29/66825
摘要： Forming a memory structure includes forming a charge storage layer over a substrate; forming a first control gate layer; patterning the first control gate layer to form an opening in the first control gate layer and the charge storage layer, wherein the opening extends into the substrate; filling the opening with an insulating material; forming a second control gate layer over the patterned first control gate layer and the insulating material; patterning the second control gate layer to form a first control gate electrode and a second control gate electrode, wherein the first control gate electrode comprises a first portion of each of the first and second control gate layers and the second control gate electrode comprises a second portion of each of the first and second control gate layers, and the insulating material is between the control gate electrodes; and forming select gate electrodes adjacent the control gate electrodes.
摘要翻译：形成存储器结构包括在衬底上形成电荷存储层; 形成第一控制栅层; 图案化第一控制栅极层以在第一控制栅极层和电荷存储层中形成开口，其中开口延伸到基板中; 用绝缘材料填充开口; 在所述图案化的第一控制栅极层和绝缘材料上形成第二控制栅极层; 图案化第二控制栅极层以形成第一控制栅电极和第二控制栅电极，其中第一控制栅电极包括第一和第二控制栅层中的每一个的第一部分，而第二控制栅电极包括第二部分并且所述绝缘材料位于所述控制栅电极之间; 以及在控制栅电极附近形成选择栅电极。

29. 发明授权

US08835295B2 Split gate memory device with gap spacer 有权
标题翻译：具有间隔垫片的分离栅存储器件
公开(公告)号：US08835295B2
公开(公告)日：2014-09-16
申请号：US13961574
申请日：2013-08-07
申请人： Jinmiao J. Shen , Ko-Min Chang , Brian A. Winstead
发明人： Jinmiao J. Shen , Ko-Min Chang , Brian A. Winstead
IPC分类号： H01L29/423
CPC分类号： H01L29/42344 , H01L21/28273 , H01L21/28282 , H01L29/42328 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A method for forming a split gate device includes forming a first sidewall of a first conductive gate layer, wherein the semiconductor layer includes a tunnel region laterally adjacent the first sidewall, forming a dielectric layer along the first sidewall to provide for increased thickness of a gap spacer, forming a charge storage layer over a portion of a top surface of the first conductive layer and over the tunnel region, and forming a second conductive gate layer over the charge storage layer.
摘要翻译：用于形成分离栅极器件的方法包括形成第一导电栅极层的第一侧壁，其中所述半导体层包括横向邻近所述第一侧壁的隧道区域，沿着所述第一侧壁形成电介质层，以提供增加的间隙厚度间隔物，在所述第一导电层的顶表面的一部分上并在所述隧道区上方形成电荷存储层，以及在所述电荷存储层上形成第二导电栅极层。

30. 发明申请

US20130320285A1 FIELD FOCUSING FEATURES IN A RERAM CELL 有权
标题翻译： RERAM细胞中的场聚焦特征
公开(公告)号：US20130320285A1
公开(公告)日：2013-12-05
申请号：US13486690
申请日：2012-06-01
申请人： Feng Zhou , Frank K. Baker, JR. , Ko-Min Chang , Cheong Min Hong
发明人： Feng Zhou , Frank K. Baker, JR. , Ko-Min Chang , Cheong Min Hong
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L45/04 , H01L45/1233 , H01L45/1246 , H01L45/1273 , H01L45/146 , H01L45/1675
摘要： A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.
摘要翻译：一种电阻随机存取存储器（ReRAM）单元，包括在第一导电电极上的第一导电电极和介电存储材料层。电介质存储材料层有利于在将细丝形成电压施加到电池时形成导电细丝。电池包括位于介电存储材料层上的第二导电电极和包括与电介质存储材料层接触并与第一导电电极或第二导电电极接触的多个纳米团簇的导电纳米团簇（911,1211）。

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