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21. 发明授权

US5777360A Hexagonal field programmable gate array architecture 失效
标题翻译：六角场可编程门阵列架构
公开(公告)号：US5777360A
公开(公告)日：1998-07-07
申请号：US517508
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L27/088 , H01L27/115
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclose. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了使用六角形细胞的细胞结构。该体系结构不限于六角形细胞。细胞可以由两个或更多个六边形的簇由三角形，平行四边形以及能够适应各种细胞形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

22. 发明授权

US5889329A Tri-directional interconnect architecture for SRAM 失效
标题翻译：用于SRAM的三向互连架构
公开(公告)号：US5889329A
公开(公告)日：1999-03-30
申请号：US517339
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L23/535
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

23. 发明授权

US5864165A Triangular semiconductor NAND gate 失效
标题翻译：三角半导体NAND门
公开(公告)号：US5864165A
公开(公告)日：1999-01-26
申请号：US517451
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L29/772
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，用于互连集成电路的微电子单元的端子的电导体优选地在彼此成角度地移位60度的三个方向上延伸。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

24. 发明授权

US5834799A Optically transmissive preformed planar structures 失效
标题翻译：光学透射预制平面结构
公开(公告)号：US5834799A
公开(公告)日：1998-11-10
申请号：US679949
申请日：1996-07-15
申请人： Michael D. Rostoker , Nicholas F. Pasch
发明人： Michael D. Rostoker , Nicholas F. Pasch
IPC分类号： G03F7/20 , H01L21/56 , H01L21/60 , H01L31/0203 , H01L31/0232 , H01L33/00 , H01L23/02
CPC分类号： G03F7/70433 , H01L21/563 , H01L24/29 , H01L24/81 , H01L31/0203 , H01L31/0232 , H01L2224/13111 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48472 , H01L2224/73203 , H01L2224/73204 , H01L2224/81193 , H01L2224/81801 , H01L2224/83101 , H01L2924/01004 , H01L2924/01005 , H01L2924/01013 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H05K2201/10424 , H05K2203/167
摘要： A semiconductor die is disposed on a side of an optically-transmissive preformed planar structure (interposer), and an optical element is disposed on an opposite side of the interposer. The interposer may be provided with through holes extending at least partially into the die side, and electrical probes in the through holes, for making contact to raised conductive bumps on the die. The interposer may be provided with raised portions for locating the optical element at a predetermined distance away from the die. The interposer may be provided with darkened areas for preventing light from impacting selected areas of the die.
摘要翻译：半导体管芯设置在光学透射的预制平面结构（插入件）的一侧，并且光学元件设置在插入件的相对侧上。插入器可以设置有至少部分地延伸到管芯侧的通孔，以及通孔中的电探针，用于与管芯上的凸起的导电凸块接触。插入器可以设置有用于将光学元件定位在离模具预定距离处的凸起部分。内插器可以设置有遮光区域，用于防止光撞击模具的选定区域。

25. 发明授权

US5554484A Gamma radiation sensitive resist materials for semiconductor lithography 失效
标题翻译：用于半导体光刻的伽马辐射敏感抗蚀剂材料
公开(公告)号：US5554484A
公开(公告)日：1996-09-10
申请号：US359046
申请日：1994-12-19
申请人： Michael D. Rostoker , Nicholas F. Pasch , Joe Zelayeta
发明人： Michael D. Rostoker , Nicholas F. Pasch , Joe Zelayeta
IPC分类号： G02B17/00 , G02B26/02 , G02B27/09 , G02F1/19 , G02F1/33 , G03F7/20 , G21K1/04 , G03F7/004
CPC分类号： G02B27/0994 , G02B17/00 , G02B26/02 , G02F1/19 , G03F7/70008 , G03F7/702 , G03F7/70375 , G21K1/04 , G02F1/33 , Y10S430/107 , Y10S430/108
摘要： Fine, sub-micron line features and patterns are created in a radiation sensitive resist layer on a semiconductor wafer by a beam of short wavelength gamma rays. The resist layer includes photoresist which is substantially chemically inactive in response to the gamma rays. The photoresist is either doped or covered with a material that absorbs gamma rays and in response emits secondary radiation of a different wavelength, preferably photons, that is actinic with respect to the photoresist. The resist layer enables using radiation sources having better resolving ability than conventional photolithographic sources to perform near-field and direct-write lithography.
摘要翻译：通过短波长γ射线束在半导体晶片上的辐射敏感抗蚀剂层中产生细的亚微米线特征和图案。抗蚀剂层包括响应于γ射线基本上化学惰性的光致抗蚀剂。光致抗蚀剂被掺杂或被吸收伽马射线的材料覆盖，并且响应于发射相对于光致抗蚀剂而光化的不同波长的次级辐射，优选光子。抗蚀剂层能够使用具有比常规光刻源更好的分辨能力的辐射源来进行近场和直写光刻。

26. 发明授权

US5478698A Direct-write afocal electron-beam semiconductor lithography 失效
标题翻译：直写无电子束半导体光刻技术
公开(公告)号：US5478698A
公开(公告)日：1995-12-26
申请号：US105261
申请日：1993-08-12
申请人： Michael D. Rostoker , Nicholas F. Pasch , Joe Zelayeta
发明人： Michael D. Rostoker , Nicholas F. Pasch , Joe Zelayeta
IPC分类号： H01J37/317 , G03F7/20 , H01J37/30
CPC分类号： B82Y15/00 , B82Y10/00 , B82Y40/00 , H01J37/3174 , H01J2237/06341 , H01J2237/31735 , Y10S430/143 , Y10S977/855
摘要： A technique is describe for effecting very-high resolution semiconductor lithography using direct-write afocal electron-beam exposure of a sensitized wafer. A positioning mechanism and needle-like probe similar to those used in scanning-tunneling microscopy are used in conjunction with a controllable electron field emission source to produce a near-field electron beam capable of exposing an electron-beam sensitive resist on a wafer surface. Conventional e-beam resists are used. The technique can be used in conjunction with scanning-tunneling-like operation of the apparatus to record the appearance and nature of the wafer surface, thereby providing information about the location of underlying features. This location information can be used to assist in aligning the exposure patterns to existing structures in the semiconductor wafer. A multi-probe embodiment with separately controllable field emission sources provides for improved productivity by permitting contemporaneous exposure of multiple sites on a single wafer.
摘要翻译：描述了一种技术，用于使用致敏晶片的直接写入无电子束曝光来实现非常高分辨率的半导体光刻。与扫描隧道显微镜中使用的类似的定位机构和针状探针与可控电子场发射源结合使用以产生能够在晶片表面上暴露电子束敏感抗蚀剂的近场电子束。使用常规电子束抗蚀剂。该技术可以与装置的扫描隧道式操作一起使用，以记录晶片表面的外观和性质，从而提供关于底层特征的位置的信息。该位置信息可用于帮助将曝光图案对准半导体晶片中的现有结构。具有单独可控的场致发射源的多探针实施例通过允许在单个晶片上同时曝光多个位置来提供提高的生产率。

27. 发明授权

US5477086A Shaped, self-aligning micro-bump structures 失效
标题翻译：形状，自对准微凸块结构
公开(公告)号：US5477086A
公开(公告)日：1995-12-19
申请号：US55429
申请日：1993-04-30
申请人： Michael D. Rostoker , Nicholas F. Pasch
发明人： Michael D. Rostoker , Nicholas F. Pasch
IPC分类号： H01L21/60 , H01L23/485 , H01L23/498 , H05K1/11 , H05K3/34 , H05K3/40 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L24/12 , H01L23/49811 , H01L23/49816 , H01L24/11 , H01L24/16 , H05K1/111 , H05K3/3436 , H05K3/4007 , H01L2221/68313 , H01L2224/13099 , H01L2224/81136 , H01L2224/81141 , H01L2224/81193 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H05K2201/09745 , H05K2201/10242 , H05K2201/10992 , H05K2203/048 , H05K3/4015 , Y02P70/611 , Y02P70/613 , Y10T428/12361
摘要： Positive mechanical alignment is provided between substrates using micro-bump contacts by forming "detented" conductive bump contacts on one substrate having a concave end which receive and align the generally convex contour of bump contacts on the other substrate. Various configurations of concavities and convexities are described. Flux may be disposed in the concave end of the detented bump contact to promote formation of joints between the concave and convex bump contacts. Both bump contacts may be formed of reflowable material, such as solder, or one or the other of the contacts may be formed of a non-reflowable material which may also function as a standoff between the two substrates. Each substrate is provided with a plurality of bump contacts, and one substrate may be provided with a combination of convex and concave bump contacts corresponding to concave and convex bump contacts on the other substrate. The inventive technique is useful for joining die-to-die, die-to-substrate, or package-to-substrate.
摘要翻译：通过在具有凹端的一个基板上形成“定位”的导电凸块触点，在衬底之间提供正的机械对准，使用微凸块触点，该凹入端接收并对准另一个基板上的凸块触点的大致凸形轮廓。描述各种凹凸的构造。通量可以设置在止动凸起接触的凹入端中，以促进凹凸凸点触点之间的接合部的形成。两个凸起触点可以由可回流材料（例如焊料）形成，或者一个或另一个触点可以由也可用作两个基板之间的间隙的不可回流材料形成。每个基板设置有多个凸块触点，并且一个基板可以设置有与另一个基板上的凹凸凸点接触对应的凸凸触点的组合。本发明的技术可用于连接管芯到管芯，管芯到衬底或封装到衬底。

28. 发明授权

US5453583A Interior bond pad arrangements for alleviating thermal stresses 失效
标题翻译：用于减轻热应力的内部粘结垫布置
公开(公告)号：US5453583A
公开(公告)日：1995-09-26
申请号：US58117
申请日：1993-05-05
申请人： Michael D. Rostoker , Nicholas F. Pasch , Joe Zelayeta
发明人： Michael D. Rostoker , Nicholas F. Pasch , Joe Zelayeta
IPC分类号： H01L23/485 , H05K1/00
CPC分类号： H01L24/06 , H01L2224/0401 , H01L2224/05554 , H01L2224/49171 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01039 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/351
摘要： A technique for reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by grouping the bond pads into a relatively small (compared to the total area of the die) sub-area within an interior area (generally away from the periphery) of the die. By keeping the bond pad layout small (tightly grouped, or oriented along a single row, or axis), differential thermally induced displacements between the bond pads are minimized, or are controlled in one dimension. Further, the bond pads may be disposed in a small area near the center of thermal expansion (centroid) of the die or near a heat-producing circuit element to minimize absolute thermal displacements of individual bond pads from the centroid or the circuit element. Overlapping sub-area patterns may be used, and grouped bond pads may be used in conjunction with (including overlapping of) traditional die-periphery located bond pads. Other aspects involve disposing the bond pads into an elongated pattern to minimize thermal displacement primarily in one direction, and orienting a lead frame or the like to accommodate any thermal migration of the bond pads in a controlled direction.
摘要翻译：减小半导体器件组件中的接合焊盘上的热诱导机械应力的技术是通过将接合焊盘分组成内部区域（通常远离外围部分）相对较小（与模具的总面积相比）的子区域）的死亡。通过保持接合焊盘布局小（紧密组合，或沿着单个行或轴定向），接合焊盘之间的差异热诱导位移被最小化，或者被控制在一个维度上。此外，接合焊盘可以设置在靠近管芯的热膨胀（中心）的中心附近的小区域中，或靠近发热电路元件，以最小化单个接合焊盘与质心或电路元件的绝对热位移。可以使用重叠的子区域图案，并且分组的接合焊盘可以与传统的芯片周边定位的焊盘结合使用（包括重叠）。其他方面涉及将接合焊盘设置成细长图案以最小化主要在一个方向上的热位移，并且定向引线框架等以适应接合焊盘在受控方向上的任何热迁移。

29. 发明授权

US5744399A Process for forming low dielectric constant layers using fullerenes 失效
标题翻译：使用富勒烯形成低介电常数层的方法
公开(公告)号：US5744399A
公开(公告)日：1998-04-28
申请号：US557721
申请日：1995-11-13
申请人： Michael D. Rostoker , Nicholas F. Pasch
发明人： Michael D. Rostoker , Nicholas F. Pasch
IPC分类号： H01L21/316 , H01L21/768
CPC分类号： H01L21/02129 , H01L21/02203 , H01L21/02271 , H01L21/02304 , H01L21/0234 , H01L21/02343 , H01L21/02362 , H01L21/31695 , H01L21/7682 , H01L21/76832 , H01L21/76829 , H01L2221/1047
摘要： A process for lowering the dielectric constant of a layer on a semiconductor wafer is described. The presence of the fullerene in the composite layer changes its dielectric constant. The process forms, on the wafer, a composite layer comprising matrix-forming material and a fullerene. The fullerene may be removed from the composite layer to leave an open porous layer. Removing the fullerene may be accomplished, for example, by contacting the composite layer with a liquid which is a solvent for the fullerene but not for the insulation material or by oxidizing the fullerene. The processes and insulation layers described are particularly useful for integrated circuits.
摘要翻译：描述了用于降低半导体晶片上的层的介电常数的方法。复合层中富勒烯的存在会改变其介电常数。该方法在晶片上形成包含基质形成材料和富勒烯的复合层。可以从复合层中除去富勒烯以留下开放的多孔层。除去富勒烯可以例如通过使复合层与作为富勒烯的溶剂而不是绝缘材料的液体或通过氧化富勒烯而接触来实现。所描述的工艺和绝缘层对集成电路特别有用。

30. 发明授权

US5696403A System having input-output drive reduction 失效
标题翻译：具有输入输出驱动减少的系统
公开(公告)号：US5696403A
公开(公告)日：1997-12-09
申请号：US626468
申请日：1996-04-02
申请人： Michael D. Rostoker , Nicholas F. Pasch
发明人： Michael D. Rostoker , Nicholas F. Pasch
IPC分类号： H01L23/522 , H01L23/552
CPC分类号： H01L23/5222 , H01L2224/48227 , H01L2924/10253 , H01L2924/13091 , H01L2924/15311
摘要： An electronic system utilizing at least one integrated circuit that has reduced drive requirements for the input and output pads of the integrated circuit die. The integrated circuit of the system has an intermediate structure added between the output connection pad and substrate to reduce the amount of electron charge required to charge the output pad capacitance of the integrated circuit to a substantially negligible amount. In addition, an intermediate structure may be added between an input connection pad and substrate of the integrated circuit to reduce the amount of electron charge required to charge the input pad capacitance to a substantially negligible amount. In the present invention, a transistor amplifier driver is connected to the intermediate structure between the output pad and substrate to charge the capacitance that exists between the intermediate structure and substrate so that the voltage potential of the intermediate structure is substantially the same value as the output pad voltage value. In similar fashion, a transistor amplifier driver is connected to the intermediate structure between the input pad and substrate to charge the capacitance that exists between the intermediate structure and substrate so that the voltage potential of the intermediate structure is substantially the same value as the input pad voltage value.
摘要翻译：一种使用至少一个集成电路的电子系统，该集成电路降低了对集成电路管芯的输入和输出焊盘的驱动要求。该系统的集成电路具有添加在输出连接焊盘和衬底之间的中间结构，以减少将集成电路的输出焊盘电容充电至基本可忽略的量所需的电子电荷量。此外，可以在输入连接焊盘和集成电路的基板之间添加中间结构，以减少将输入焊盘电容充电至基本可忽略的量所需的电子电荷量。在本发明中，晶体管放大器驱动器连接到输出焊盘和衬底之间的中间结构，以对存在于中间结构和衬底之间的电容进行充电，使得中间结构的电压电位基本上与输出的值相同焊盘电压值。以类似的方式，晶体管放大器驱动器连接到输入焊盘和衬底之间的中间结构，以对存在于中间结构和衬底之间的电容进行充电，使得中间结构的电压电位与输入焊盘基本相同电压值。

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