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21. 发明申请

US20100117137A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20100117137A1
公开(公告)日：2010-05-13
申请号：US12559865
申请日：2009-09-15
申请人： Yoshiaki FUKUZUMI , Masaru KITO , Ryota KATSUMATA , Masaru KIDOH , Hiroyasu TANAKA , Yosuke KOMORI , Megumi ISHIDUKI , Hideaki AOCHI
发明人： Yoshiaki FUKUZUMI , Masaru KITO , Ryota KATSUMATA , Masaru KIDOH , Hiroyasu TANAKA , Yosuke KOMORI , Megumi ISHIDUKI , Hideaki AOCHI
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11578 , H01L21/28282 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： Each of memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate; a charge storage layer formed to surround a side surface of the columnar portions; and a first conductive layer formed to surround the charge storage layer. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; a gate insulating layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the gate insulating layer. An effective impurity concentration of the second semiconductor layer is less than or equal to an effective impurity concentration of the first semiconductor layer.
摘要翻译：每个存储器串都具有第一半导体层，该第一半导体层具有相对于衬底沿垂直方向延伸的一对柱状部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕电荷存储层的第一导电层。每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 形成为围绕所述第二半导体层的侧表面的栅极绝缘层; 以及形成为围绕所述栅极绝缘层的第二导电层。第二半导体层的有效杂质浓度小于或等于第一半导体层的有效杂质浓度。

22. 发明申请

US20080203378A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20080203378A1
公开(公告)日：2008-08-28
申请号：US12037402
申请日：2008-02-26
申请人： Hiroyasu TANAKA , Mitsuru SATO , Ryota KATSUMATA , Masaru KIDOH , Masaru KITO , Hideaki AOCHI
发明人： Hiroyasu TANAKA , Mitsuru SATO , Ryota KATSUMATA , Masaru KIDOH , Masaru KITO , Hideaki AOCHI
IPC分类号： H01L47/00 , H01L21/00 , H01L21/336
CPC分类号： H01L45/144 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C2213/31 , G11C2213/32 , G11C2213/75 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/146 , H01L45/1675
摘要： A phase change memory device including plural memory cells is disclosed. Each of the memory cells includes memory transistors and phase change film portions formed above or below the memory transistors. The phase change film portions correspond to the respective memory transistors respectively. Vias are provided in order to connect each of the memory transistor in parallel to each of the phase change film portions in each of the memory cells. The vias connect the memory cells in series to one another.
摘要翻译：公开了一种包括多个存储单元的相变存储器件。每个存储单元包括形成在存储晶体管的上方或下方的存储晶体管和相变膜部分。相变膜部分别对应于相应的存储晶体管。提供通孔，以将存储晶体管中的每一个与每个存储单元中的每个相变膜部分并联连接。通孔将存储单元串联连接。

23. 发明申请

US20120218821A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20120218821A1
公开(公告)日：2012-08-30
申请号：US13463889
申请日：2012-05-04
申请人： Kiyotaro ITAGAKI , Yoshihisa IWATA , Hiroyasu TANAKA , Masaru KIDOH , Masaru KITO , Ryota KATSUMATA , Hideaki AOCHI , Akihiro NITAYAMA , Takashi MAEDA , Tomoo HISHIDA
发明人： Kiyotaro ITAGAKI , Yoshihisa IWATA , Hiroyasu TANAKA , Masaru KIDOH , Masaru KITO , Ryota KATSUMATA , Hideaki AOCHI , Akihiro NITAYAMA , Takashi MAEDA , Tomoo HISHIDA
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/30
摘要： A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.
摘要翻译：非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。一定的电位差是导致GIDL电流的电位差。

24. 发明申请

US20130075805A1 METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：制造非易失性半导体存储器件和非易失性半导体存储器件的方法
公开(公告)号：US20130075805A1
公开(公告)日：2013-03-28
申请号：US13419984
申请日：2012-03-14
申请人： Mitsuru SATO , Megumi ISHIDUKI , Masaru KIDOH , Atsushi KONNO , Yoshihiro AKUTSU , Masaru KITO , Yoshiaki FUKUZUMI , Ryota KATSUMATA
发明人： Mitsuru SATO , Megumi ISHIDUKI , Masaru KIDOH , Atsushi KONNO , Yoshihiro AKUTSU , Masaru KITO , Yoshiaki FUKUZUMI , Ryota KATSUMATA
IPC分类号： H01L29/792 , H01L21/425
CPC分类号： H01L29/7926 , H01L21/265 , H01L27/11582 , H01L29/0676 , H01L29/66833
摘要： According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion.
摘要翻译：根据一个实施例，一种用于制造非易失性半导体存储装置的方法包括：形成第一和第二堆叠体; 形成穿过所述第一层叠体的通孔，与所述第一部分连通并穿过选择栅极的第二部分，以及与所述第二部分连通并穿透第二绝缘层的第三部分; 形成记忆膜，栅极绝缘膜和通道体; 在通道体内形成第三绝缘层; 在第三部分内部的边界部分上方形成第一嵌入部分; 通过去除第三部分中的第一嵌入部分和第三绝缘层的一部分的一部分来暴露通道体; 以及在所述第三部分内部嵌入包含比所述第一嵌入部分上方的所述第一嵌入部分杂质浓度高的硅的第二嵌入部分。

25. 发明申请

US20100052042A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100052042A1
公开(公告)日：2010-03-04
申请号：US12561451
申请日：2009-09-17
申请人： Hiroyasu TANAKA , Ryota KATSUMATA , Hideaki AOCHI , Masaru KIDO , Masaru KITO , Mitsuru SATO
发明人： Hiroyasu TANAKA , Ryota KATSUMATA , Hideaki AOCHI , Masaru KIDO , Masaru KITO , Mitsuru SATO
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/7881 , H01L29/7926
摘要： The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.
摘要翻译：本发明的半导体存储器件包括具有串联连接的多个电可再编程存储器单元的多个存储器串，具有列形半导体的存储器串，形成在柱状半导体周围的第一绝缘膜，电荷累积层形成在第一绝缘膜周围，形成在电荷累积膜周围的第二绝缘膜和围绕第二绝缘膜形成的多个电极，经由多个选择晶体管连接到存储器串的一端的位线，以及导电分别在存储器串的多个电极和不同的存储器串的多个电极中分别共享，其中导电层的每个端部在平行于位线的方向上形成为台阶形状。

26. 发明申请

US20070290253A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20070290253A1
公开(公告)日：2007-12-20
申请号：US11765881
申请日：2007-06-20
申请人： Masaru KITO , Nobutoshi Aoki , Masaru Kidoh , Ryota Katsumata , Masaki Kondo , Naoki Kusunoki , Toshiyuki Enda , Sanae Ito , Hiroyoshi Tanimoto , Hideaki Aochi , Akihiro Nitayama , Riichiro Shirota
发明人： Masaru KITO , Nobutoshi Aoki , Masaru Kidoh , Ryota Katsumata , Masaki Kondo , Naoki Kusunoki , Toshiyuki Enda , Sanae Ito , Hiroyoshi Tanimoto , Hideaki Aochi , Akihiro Nitayama , Riichiro Shirota
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/42336
摘要： A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.
摘要翻译：非易失性半导体存储器件包括：半导体区域; 器件隔离区域放置在半导体区域中并沿列方向延伸; 放置在半导体区域和器件隔离区之间的半导体层，沿着行方向具有凸形的横截面; 源极/漏极区域放置在半导体层中并彼此间隔开; 位于源极/漏极区之间的半导体层上的栅极绝缘膜; 放置在栅极绝缘膜上的浮栅电极层; 布置在浮栅电极层和器件隔离区的上表面上的隔间绝缘膜; 以及控制栅极电极层，其设置在所述隔间绝缘膜上并沿行方向延伸。

27. 发明申请

US20080087957A1 Semiconductor Device and Method for Fabricating Semiconductor Device 有权
标题翻译：用于制造半导体器件的半导体器件和方法
公开(公告)号：US20080087957A1
公开(公告)日：2008-04-17
申请号：US11868051
申请日：2007-10-05
申请人： Ryota KATSUMATA , Hideaki AOCHI , Masaru KIDOH , Masaru KITO
发明人： Ryota KATSUMATA , Hideaki AOCHI , Masaru KIDOH , Masaru KITO
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/266 , H01L29/1083 , H01L29/49 , H01L29/6659 , H01L29/7833
摘要： According to an aspect of the present invention, there is provided a semiconductor device including a first conductive type semiconductor substrate, a gate electrode formed over the semiconductor substrate via a gate insulator, a first conductive impurity region buried in the semiconductor substrate, the first conductive impurity region being both sides of an extend plane, the extend plane being extended from side-walls of the gate electrode into the semiconductor substrate and a second conductive type source/drain region partially overlapping with the first conductive impurity region and extending from an end of the gate electrode at the semiconductor substrate to an outer region in the semiconductor substrate, wherein a first conductive impurity concentration at a prescribed depth in the overlapping portion between the first conductive impurity region and the source/drain region is lower than the first conductive impurity concentration in the first conductive impurity region except the overlapping portion corresponding to the prescribed depth.
摘要翻译：根据本发明的一个方面，提供了一种半导体器件，包括第一导电型半导体衬底，通过栅绝缘体形成在半导体衬底上的栅电极，埋在半导体衬底中的第一导电杂质区，第一导电杂质区域是延伸平面的两侧，所述延伸平面从所述栅电极的侧壁延伸到所述半导体衬底中，以及与所述第一导电杂质区域部分重叠并从所述第一导电杂质区域的一端延伸的第二导电型源极/ 半导体衬底上的栅极电极到半导体衬底中的外部区域，其中在第一导电杂质区域和源极/漏极区域之间的重叠部分中在规定深度处的第一导电杂质浓度低于第一导电杂质浓度在除t外的第一导电杂质区他的重叠部分对应于规定的深度。

28. 发明申请

US20080017922A1 Semiconductor Device and Manufacturing Method Thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080017922A1
公开(公告)日：2008-01-24
申请号：US11688449
申请日：2007-03-20
申请人： Masaru KITO , Hideaki AOCHI , Ryota KATSUMATA , Masaru KIDOH
发明人： Masaru KITO , Hideaki AOCHI , Ryota KATSUMATA , Masaru KIDOH
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/0605 , H01L21/8221 , H01L21/84 , H01L27/12
摘要： A semiconductor device having a first semiconductor region and second semiconductor region including impurities formed on an insulating layer formed on a semiconductor substrate, an insulator formed between the first semiconductor region and the second semiconductor region, a first impurity diffusion control film formed on the first semiconductor region and a second impurity diffusion control film formed on the second semiconductor region, a channel layer formed on the first impurity diffusion control film and second impurity diffusion film to cross at right angles with a direction where the first semiconductor region and the second semiconductor region are extended, a gate insulating film formed on the channel layer and a gate electrode formed on the gate insulating layer.
摘要翻译：一种具有第一半导体区域和第二半导体区域的半导体器件，所述第二半导体区域包括形成在形成于半导体衬底上的绝缘层上的杂质，形成在所述第一半导体区域和所述第二半导体区域之间的绝缘体，形成在所述第一半导体区域和形成在第二半导体区域上的第二杂质扩散控制膜，形成在第一杂质扩散控制膜和第二杂质扩散膜上的沟道层，以与第一半导体区域和第二半导体区域的方向成直角交叉扩展了形成在沟道层上的栅极绝缘膜和形成在栅极绝缘层上的栅电极。

29. 发明申请

US20100295116A1 Semiconductor Device and Manufacturing Method Thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100295116A1
公开(公告)日：2010-11-25
申请号：US12850783
申请日：2010-08-05
申请人： Masaru KITO , Hideaki AOCHI , Ryota KATSUMATA , Masaru KIDOH
发明人： Masaru KITO , Hideaki AOCHI , Ryota KATSUMATA , Masaru KIDOH
IPC分类号： H01L29/792
CPC分类号： H01L27/0605 , H01L21/8221 , H01L21/84 , H01L27/12
摘要： A semiconductor device having a first semiconductor region and second semiconductor region including impurities formed on an insulating layer formed on a semiconductor substrate, an insulator formed between the first semiconductor region and the second semiconductor region, a first impurity diffusion control film formed on the first semiconductor region and a second impurity diffusion control film formed on the second semiconductor region, a channel layer formed on the first impurity diffusion control film and second impurity diffusion film to cross at right angles with a direction where the first semiconductor region and the second semiconductor region are extended, a gate insulating film formed on the channel layer and a gate electrode formed on the gate insulating layer.
摘要翻译：一种具有第一半导体区域和第二半导体区域的半导体器件，所述第二半导体区域包括形成在形成于半导体衬底上的绝缘层上的杂质，形成在所述第一半导体区域和所述第二半导体区域之间的绝缘体，形成在所述第一半导体区域和形成在第二半导体区域上的第二杂质扩散控制膜，形成在第一杂质扩散控制膜和第二杂质扩散膜上的沟道层，以与第一半导体区域和第二半导体区域的方向成直角交叉扩展了形成在沟道层上的栅极绝缘膜和形成在栅极绝缘层上的栅电极。

30. 发明申请

US20130020627A1 SHIFT REGISTER MEMORY AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：移位寄存器及其制造方法
公开(公告)号：US20130020627A1
公开(公告)日：2013-01-24
申请号：US13409652
申请日：2012-03-01
申请人： Yoshiaki FUKUZUMI , Masaru KITO , Tomoko FUJIWARA , Kaori KAWASAKI , Hideaki AOCHI
发明人： Yoshiaki FUKUZUMI , Masaru KITO , Tomoko FUJIWARA , Kaori KAWASAKI , Hideaki AOCHI
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L21/84 , G11C19/00 , H01L27/10 , H01L27/11517 , H01L27/1203
摘要： In one embodiment, a shift register memory includes first and second control electrodes extending in a first direction parallel to a surface of a substrate, and facing each other in a second direction perpendicular to the first direction. The memory further includes a plurality of first floating electrodes provided in a line on a first control electrode side between the first and second control electrodes. The memory further includes a plurality of second floating electrodes provided in a line on a second control electrode side between the first and second control electrodes. Each of the first and second floating electrodes has a planar shape which is mirror-asymmetric with respect to a plane perpendicular to the first direction.
摘要翻译：在一个实施例中，移位寄存器存储器包括在平行于衬底表面的第一方向上延伸的第一和第二控制电极，并且在垂直于第一方向的第二方向上彼此面对。存储器还包括设置在第一和第二控制电极之间的第一控制电极侧的一行中的多个第一浮置电极。存储器还包括设置在第一和第二控制电极之间的第二控制电极侧的一行中的多个第二浮置电极。第一和第二浮动电极中的每一个具有相对于垂直于第一方向的平面镜像不对称的平面形状。

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