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21. 发明授权

US06770938B1 Diode fabrication for ESD/EOS protection 有权
标题翻译：用于ESD / EOS保护的二极管制造
公开(公告)号：US06770938B1
公开(公告)日：2004-08-03
申请号：US10050394
申请日：2002-01-16
申请人： Michael Fliesler , Mark Ramsbey , Mark Randolph , Ian Morgan , Timothy Thurgate , Paohua Kuo , David M. Rogers
发明人： Michael Fliesler , Mark Ramsbey , Mark Randolph , Ian Morgan , Timothy Thurgate , Paohua Kuo , David M. Rogers
IPC分类号： H01L2362
CPC分类号： H01L27/0255
摘要： An ESD protection device is provided for an integrated circuit. The ESD protection device includes a power supply clamp device formed from a diode and coupled between a first power supply VCC and a second power supply VSS. An input protection device is also provided which is formed from a diode coupled between an input pad and the first power supply and a second diode coupled between the input pad and a second power supply. The diodes have an adjusted reverse breakdown voltage that is higher than the voltage supply VCC used to power the peripheral circuitry that drives circuitry within a core of the integrated circuit. The adjusted reverse breakdown voltage is also lower than the breakdown voltage of gate oxide layers used within the peripheral circuitry.
摘要翻译：为集成电路提供ESD保护装置。 ESD保护装置包括由二极管形成并耦合在第一电源VCC和第二电源VSS之间的电源钳位装置。还提供一种输入保护装置，其由耦合在输入焊盘和第一电源之间的二极管和耦合在输入焊盘和第二电源之间的第二二极管形成。二极管具有调整的反向击穿电压，其高于用于为驱动集成电路的核心内的电路的外围电路供电的电压源VCC。调整的反向击穿电压也低于在外围电路中使用的栅极氧化物层的击穿电压。

22. 发明授权

US06486029B1 Integration of an ion implant hard mask structure into a process for fabricating high density memory cells 有权
标题翻译：将离子注入硬掩模结构集成到用于制造高密度存储器单元的工艺中
公开(公告)号：US06486029B1
公开(公告)日：2002-11-26
申请号：US09627563
申请日：2000-07-28
申请人： David K. Foote , Bharath Rangarajan , Stephan K. Park , Fei Wang , Dawn M. Hopper , Jack Thomas , Mark Chang , Mark Ramsbey
发明人： David K. Foote , Bharath Rangarajan , Stephan K. Park , Fei Wang , Dawn M. Hopper , Jack Thomas , Mark Chang , Mark Ramsbey
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/954
摘要： A process for fabricating a memory cell in a two-bit EEPROM device, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. Preferably, the hard mask includes a material selected from the group consisting of tungsten, titanium, titanium nitride, polysilicon, silicon, silicon nitride, silicon oxi-nitride, and silicon rich nitride. In one preferred embodiment, the process further includes implanting the semiconductor substrate with a p-type dopant at an angle substantially normal to the principal surface of the semiconductor substrate and annealing the semiconductor substrate upon implanting the semiconductor substrate with a p-type dopant. In one preferred embodiment, the process further includes implanting the semiconductor substrate with an n-type dopant.
摘要翻译：一种用于在2位EEPROM器件中制造存储单元的工艺，该工艺包括形成覆盖半导体衬底的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。优选地，硬掩模包括选自钨，钛，氮化钛，多晶硅，硅，氮化硅，氧化氮化硅和富氮的氮化物的材料。在一个优选实施例中，该方法还包括以基本上垂直于半导体衬底的主表面的角度注入具有p型掺杂剂的半导体衬底，并在用p型掺杂剂注入半导体衬底时退火半导体衬底。在一个优选实施例中，该工艺还包括用n型掺杂剂注入半导体衬底。

23. 发明授权

US06410443B1 Method for removing semiconductor ARC using ARC CMP buffing 有权
标题翻译：使用ARC CMP抛光去除半导体ARC的方法
公开(公告)号：US06410443B1
公开(公告)日：2002-06-25
申请号：US09507810
申请日：2000-02-22
申请人： Steven C. Avanzino , Stephen Keetai Park , Kashmir S. Sahota , David H. Matsumoto , Mark Ramsbey
发明人： Steven C. Avanzino , Stephen Keetai Park , Kashmir S. Sahota , David H. Matsumoto , Mark Ramsbey
IPC分类号： H01L21302
CPC分类号： H01L21/76897 , H01L21/31053 , H01L2924/3011
摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten conductive contacts formed therein. In one embodiment, a chemical-mechanical polishing (CMP) process with non-oxidizer containing slurry is used to selectively remove the ARC layer at a rate which is significantly faster than the removal rates of the dielectric layer or the tungsten contacts. Further, an ARC CMP buffing process is used with a soft buffing pad in the CMP process to buff the dielectric layer and tungsten contacts during the ARC layer removal.
摘要翻译：本发明提供一种用于在基板表面上从电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨导电触头。在一个实施例中，使用含有非氧化剂的浆料的化学 - 机械抛光（CMP）工艺以比电介质层或钨接触的去除速度显着更快的速率选择性地去除ARC层。此外，ARC CMP抛光工艺与CMP抛光垫一起使用，以在ARC层去除期间抛光电介质层和钨触点。

24. 发明授权

US06362051B1 Method of forming ONO flash memory devices using low energy nitrogen implantation 有权
标题翻译：使用低能氮注入形成ONO闪存器件的方法
公开(公告)号：US06362051B1
公开(公告)日：2002-03-26
申请号：US09648361
申请日：2000-08-25
申请人： Jean Yang , Yider Wu , Hidehiko Shiraiwa , Mark Ramsbey
发明人： Jean Yang , Yider Wu , Hidehiko Shiraiwa , Mark Ramsbey
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L21/26533 , H01L21/28282 , H01L21/3144 , H01L29/513 , H01L29/518
摘要： A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide at less than normal energy levels to reduce the amount of damage to the underlying semiconductor substrate. After low energy nitrogen implantation, the semiconductor structure is heated to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds is desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.
摘要翻译：用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极第二层氧化硅。氮以低于正常能级注入到第一氧化硅层中以减少对下面的半导体衬底的损伤量。在低能量氮注入之后，半导体结构被加热以退出注入损伤并将注入的氮扩散到衬底和氧化硅界面，以在该界面处形成SiN键。 SiN键是理想的，因为它们改善了界面处的结合强度，并且保留在氧化硅层中的氮增加了氧化物体的可靠性。

25. 发明申请

US20060151821A1 Memory device having trapezoidal bitlines and method of fabricating same 有权
公开(公告)号：US20060151821A1
公开(公告)日：2006-07-13
申请号：US11033588
申请日：2005-01-12
申请人： Ashot Melik-Martirosian , Mark Ramsbey , Mark Randolph
发明人： Ashot Melik-Martirosian , Mark Ramsbey , Mark Randolph
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.

26. 发明授权

US07033957B1 ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices 有权
标题翻译： ONO制造工艺，用于增加闪存器件底部氧化物 - 衬底界面的氧含量
公开(公告)号：US07033957B1
公开(公告)日：2006-04-25
申请号：US10358586
申请日：2003-02-05
申请人： Hidehiko Shiraiwa , Tazrien Kamal , Mark Ramsbey , Inkuk Kang , Jaeyong Park , Rinji Sugino , Jean Y. Yang , Fred T K Cheung , Arvind Halliyal , Amir H. Jafarpour
发明人： Hidehiko Shiraiwa , Tazrien Kamal , Mark Ramsbey , Inkuk Kang , Jaeyong Park , Rinji Sugino , Jean Y. Yang , Fred T K Cheung , Arvind Halliyal , Amir H. Jafarpour
IPC分类号： H01L21/31
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/3144 , H01L29/513 , H01L29/792 , Y10S438/954
摘要： Process for reducing charge leakage in a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on the semiconductor substrate to form an oxide/silicon interface having a first oxygen content adjacent the oxide/silicon interface; treating the bottom oxide layer to increase the first oxygen content to a second oxygen content adjacent the oxide/silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer. In another embodiment, process for reducing charge leakage in a SONOS flash memory device, including forming a bottom oxide layer of an ONO structure on a surface of the semiconductor substrate having an oxide/silicon interface with a super-stoichiometric oxygen content adjacent the oxide/silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer.
摘要翻译：包括在一个实施例中，在半导体衬底上形成ONO结构的底部氧化物层以形成具有与氧化物/硅界面相邻的第一氧含量的氧化物/硅界面的方法，用于减少SONOS闪速存储器件中的电荷泄漏的方法; 处理底部氧化物层以将第一氧含量增加到邻近氧化物/硅界面的第二氧含量; 以及在底部氧化物层上沉积氮化物电荷存储层。在另一个实施方案中，用于减少SONOS闪速存储器件中的电荷泄漏的方法，包括在半导体衬底的表面上形成具有超化学计量氧含量的氧化物/硅界面的氧化物/硅界面的氧化物/ 硅界面; 以及在底部氧化物层上沉积氮化物电荷存储层。

27. 发明申请

US20060035459A1 Method of forming narrowly spaced flash memory contact openings and lithography masks 有权
公开(公告)号：US20060035459A1
公开(公告)日：2006-02-16
申请号：US10916167
申请日：2004-08-11
申请人： Emmanuil Lingunis , Ning Cheng , Mark Ramsbey , Kouros Ghandehari , Anna Minvielle , Hung-Eil Kim
发明人： Emmanuil Lingunis , Ning Cheng , Mark Ramsbey , Kouros Ghandehari , Anna Minvielle , Hung-Eil Kim
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L27/11568 , G03F1/36 , H01L27/115 , Y10S438/942 , Y10S438/947
摘要： A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of optical features spaced on the lithography mask from one another along a first direction, where the individual optical features have first mask feature dimensions along the first direction that are smaller than a desired first dimension for the openings to be patterned in the etch mask.

28. 发明授权

US06855608B1 Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance 失效
标题翻译：制造平面结构电荷捕获具有矩形栅极的存储单元阵列并降低位线电阻的方法
公开(公告)号：US06855608B1
公开(公告)日：2005-02-15
申请号：US10463643
申请日：2003-06-17
申请人： Mark Ramsbey , Mark W. Randolph , Jean Yee-Mei Yang , Hiroyuki Kinoshita , Cyrus Tabery , Jeff P. Erhardt , Tazrien Kamal , Jaeyong Park , Emmanuil H. Lingunis
发明人： Mark Ramsbey , Mark W. Randolph , Jean Yee-Mei Yang , Hiroyuki Kinoshita , Cyrus Tabery , Jeff P. Erhardt , Tazrien Kamal , Jaeyong Park , Emmanuil H. Lingunis
IPC分类号： G11C16/04 , H01L21/336 , H01L21/8246 , H01L27/105
CPC分类号： H01L27/11568 , G11C16/0475 , G11C16/0491 , H01L27/105 , H01L27/11573
摘要： A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates comprises fabricating a multi-layer charge trapping dielectric on the surface of a substrate. The layer adjacent to the substrate may be an oxide. A polysilicon layer is deposited over the charge trapping dielectric. A word line mask is applied over the polysilicon layer to mask linear word lines in a first direction and to expose trench regions there between and the trenches are etched to expose the charge trapping dielectric in the trench regions. A bit line mask is applied over the polysilicon layer to mask gates in a second direction perpendicular to the first direction and to expose bit line regions there between and the bit lines are etched to expose the oxide in the bit line regions. The bit lines are implanted and insulating spacers are fabricated on exposed sidewalls. The oxide is removed to expose the substrate between insulating spacers in the bit line regions and a conductor is fabricated thereon to enhance conductivity of each bit line.
摘要翻译：制造具有矩形栅极的平面架构电荷俘获介质存储单元阵列的方法包括在衬底的表面上制造多层电荷俘获电介质。与衬底相邻的层可以是氧化物。在电荷捕获电介质上沉积多晶硅层。在多晶硅层上施加字线掩模以在第一方向上屏蔽线性字线并且在其间露出沟槽区域，并且蚀刻沟槽以暴露沟槽区域中的电荷俘获电介质。将位线掩模施加在多晶硅层上以在垂直于第一方向的第二方向上屏蔽栅极，并在其间暴露位线区域，并蚀刻位线以暴露位线区域中的氧化物。植入位线，并在暴露的侧壁上制造绝缘间隔物。去除氧化物以在位线区域中的绝缘间隔物之间露出衬底，并且在其上制造导体以增强每个位线的导电性。

29. 发明授权

US06433383B1 Methods and arrangements for forming a single interpoly dielectric layer in a semiconductor device 有权
标题翻译：在半导体器件中形成单个互间电介质层的方法和布置
公开(公告)号：US06433383B1
公开(公告)日：2002-08-13
申请号：US09357333
申请日：1999-07-20
申请人： Mark Ramsbey , Unsoon Kim , Kenneth Wo-Wai Au , David H. Chi , James Markarian
发明人： Mark Ramsbey , Unsoon Kim , Kenneth Wo-Wai Au , David H. Chi , James Markarian
IPC分类号： H01L27108
CPC分类号： H01L27/11521 , H01L21/3144 , H01L21/3145 , H01L27/115 , H01L29/511
摘要： A single interpoly dielectric layer is provided for use in semiconductor devices. The single interpoly dielectric layer being formed of silicon graded such that certain regions within the single interpoly dielectric layer are either oxygen-rich or nitrogen-rich. The single interpoly dielectric layer can be formed in-situ within a single deposition tool. In certain embodiments, the resulting single interpoly dielectric layer can be made thinner and/or can be formed to provide improved dielectric characteristics when compared to a conventional oxide-nitride-oxide (ONO) interpoly dielectric layer that has three separate and unique layers. Thus, the single interpoly dielectric layer is highly desirable for use in reduced-size semiconductor devices and/or semiconductor devices requiring improved data retention capabilities, such as non-volatile memory cells.
摘要翻译：提供了一个用于半导体器件的单互补电介质层。由硅分级形成的单个间隔电介质层使得单个互间介电层内的某些区域是富氧或富含氮的。单个间隔电介质层可以在单个沉积工具内原位形成。在某些实施例中，当与具有三个独立且独特的层的常规氧化物 - 氮化物 - 氧化物（ONO）间隔电介质层相比时，所得到的单个间隔电介质层可以制成更薄和/或可形成以提供改善的介电特性。因此，对于需要改进的数据保持能力的尺寸较小的半导体器件和/或半导体器件（例如非易失性存储器单元），单个互聚电介质层是非常需要的。

30. 发明授权

US5869385A Selectively oxidized field oxide region 失效
标题翻译：选择性氧化场氧化物区域
公开(公告)号：US5869385A
公开(公告)日：1999-02-09
申请号：US569704
申请日：1995-12-08
申请人： Yuan Tang , Mark Ramsbey
发明人： Yuan Tang , Mark Ramsbey
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/76
CPC分类号： H01L21/823481 , H01L21/76213 , Y10S148/138 , Y10S438/964
摘要： A field oxide region is formed with a reduced bird's beak by selectively implanting impurity atoms into the semiconductor substrate to increase the oxidation rate of the substrate and thermally oxidizing the implanted region of the semiconductor substrate. In another embodiment, a gate oxide layer having a differential thickness is formed by implanting impurity atoms into the semiconductor substrate in a selected region wherein a thick portion of the gate oxide is to be formed and thermally oxidizing the semiconductor substrate.
摘要翻译：通过选择性地将杂质原子注入到半导体衬底中以增加衬底的氧化速率并对半导体衬底的注入区域进行热氧化，形成具有缩小的鸟嘴的场氧化物区域。在另一个实施例中，通过在要形成栅极氧化物的厚部分并对半导体衬底进行热氧化的选定区域中将杂质原子注入到半导体衬底中，形成具有差分厚度的栅氧化层。

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