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21. 发明授权

US5904539A Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties 失效
标题翻译：半导体沟槽隔离工艺导致硅台面具有增强的机械和电学性能
公开(公告)号：US5904539A
公开(公告)日：1999-05-18
申请号：US619004
申请日：1996-03-21
申请人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
发明人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , Y10S148/05
摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.
摘要翻译：提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。隔离过程产生具有增强的机械和电性能的硅台面。通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

22. 发明授权

US5895955A MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch 失效
标题翻译： MOS晶体管采用可移除的双层蚀刻停止件，以保护植入区域免受侧壁间隔物过蚀刻
公开(公告)号：US5895955A
公开(公告)日：1999-04-20
申请号：US781451
申请日：1997-01-10
申请人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L29/78 , H01L29/72
CPC分类号： H01L29/6659 , H01L29/7833 , H01L29/665
摘要： A transistor and transistor fabrication method are presented where a sequence of layers are formed and either entirely or partially removed upon sidewall surfaces of a gate conductor. The formation and removal of layers produces a series of laterally spaced surfaces to which various implants can be aligned. Those implants, placed in succession produce a highly graded junction having a relatively smooth doping profile. The multilayer spacer structure comprises a polysilicon spacer interposed between a grown oxide and an etch stop. The polysilicon spacer is formed by an anisotropic etch, and the pre-existing etch stop prevents the anisotropic etch from damaging the source/drain and gate conductor regions beneath the etch stop. Further, the etch stop allows removal of the overlying oxide as well as the entire polysilicon during times when the multi-layer spacer is entirely removed. Removal of the various layers does not damage the underlying substrate due to the presence of the etch stop. The etch stop preferably comprises a nitride layer overlying an oxide layer, wherein the oxide layer can either be deposited or grown.
摘要翻译：提出了一种晶体管和晶体管制造方法，其中形成一系列层，并且在栅极导体的侧壁表面上完全或部分地去除层。层的形成和去除产生一系列横向间隔开的表面，各种植入物可以对齐。连续放置的那些植入物产生具有相对平滑的掺杂分布的高度梯度的结。多层间隔结构包括插入生长的氧化物和蚀刻停止层之间的多晶硅间隔物。通过各向异性蚀刻形成多晶硅间隔物，并且预先存在的蚀刻停止物防止各向异性蚀刻损坏蚀刻停止点下面的源极/漏极和栅极导体区域。此外，在完全去除多层间隔物的时间期间，蚀刻停止允许去除上覆氧化物以及整个多晶硅。由于存在蚀刻停止，各层的去除不会损坏下面的衬底。蚀刻停止件优选地包括覆盖氧化物层的氮化物层，其中氧化物层可以沉积或生长。

23. 发明授权

US5861335A Semiconductor fabrication employing a post-implant anneal within a low temperature high pressure nitrogen ambient to improve channel and gate oxide reliability 失效
标题翻译：半导体制造采用在低温高压氮气环境中的植入后退火以改善沟道和栅极氧化物的可靠性
公开(公告)号：US5861335A
公开(公告)日：1999-01-19
申请号：US822122
申请日：1997-03-21
申请人： Fred N. Hause , Mark I. Gardner
发明人： Fred N. Hause , Mark I. Gardner
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/51 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/28176 , H01L21/823418 , H01L29/518 , H01L29/6659
摘要： An integrated circuit is formed with minimal encroachment of lightly doped drain (LDD) implants partially due to barrier atoms incorporated along the migration avenues. Nitrogen is incorporated either during the LDD implant or during an anneal cycle following the LDD implant. Nitrogen helps minimize segregation and diffusion of LDD dopants placed adjacent critical channel and gate dielectric areas. Nitrogen is incorporated within a chamber while under pressure so as to minimize the temperature needed to repair implant damage and activate the LDD dopants. High pressure indoctrination of nitrogen is believed to provide the same amount of lattice repair and activation achieved if anneal temperatures were substantially higher.
摘要翻译：形成集成电路，其部分原因是由于沿着迁移通道并入的屏障原子，轻掺杂漏极（LDD）植入物的侵入最小。在LDD植入期间或在LDD植入物之后的退火循环期间也掺入氮。氮有助于最小化邻近关键通道和栅极电介质区域放置的LDD掺杂物的分离和扩散。氮气在压力下并入室内，以便最小化修复植入物损伤和激活LDD掺杂剂所需的温度。如果退火温度显着较高，则认为氮气的高压灌注可提供相同量的晶格修复和激活。

24. 发明授权

US06288432B1 Semiconductor fabrication employing a post-implant anneal within a low temperature, high pressure nitrogen ambient to improve channel and gate oxide reliability 有权
标题翻译：半导体制造采用在低温，高压氮气环境中的植入后退火以改善沟道和栅极氧化物的可靠性
公开(公告)号：US06288432B1
公开(公告)日：2001-09-11
申请号：US09481808
申请日：2000-01-11
申请人： Fred N. Hause , Mark I. Gardner
发明人： Fred N. Hause , Mark I. Gardner
IPC分类号： H01L2976
CPC分类号： H01L29/7833 , H01L21/28176 , H01L21/823418 , H01L29/518 , H01L29/6659
摘要： An integrated circuit is formed with minimal encroachment of lightly doped drain (LDD) implants partially due to barrier atoms incorporated along the migration avenues. Nitrogen is incorporated either during the LDD implant or during an anneal cycle following the LDD implant. Nitrogen helps minimize segregation and diffusion of LDD dopants placed adjacent critical channel and gate dielectric areas. Nitrogen is incorporated within a chamber while under pressure so as to minimize the temperature needed to repair implant damage and activate the LDD dopants. High pressure indoctrination of nitrogen is believed to provide the same amount of lattice repair and activation achieved if anneal temperatures were substantially higher.
摘要翻译：形成集成电路，其部分原因是由于沿着迁移通道并入的屏障原子，轻掺杂漏极（LDD）植入物的侵入最小。在LDD植入期间或在LDD植入物之后的退火循环期间也掺入氮。氮有助于最小化邻近关键通道和栅极电介质区域放置的LDD掺杂物的分离和扩散。氮气在压力下并入室内，以便最小化修复植入物损伤和激活LDD掺杂剂所需的温度。如果退火温度显着较高，则认为氮气的高压灌注可提供相同量的晶格修复和激活。

25. 发明授权

US06184566B2 Method and structure for isolating semiconductor devices after transistor formation 失效
标题翻译：在晶体管形成之后隔离半导体器件的方法和结构
公开(公告)号：US06184566B2
公开(公告)日：2001-02-06
申请号：US09150776
申请日：1998-09-10
申请人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L2176
CPC分类号： H01L21/823418 , H01L21/76237 , H01L21/823425 , H01L21/823481 , Y10S257/90
摘要： A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes laterally displaced source/drain regions and channel regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. The first and second transistors have a common source/drain region. An isolation trench is formed through the common source/drain region and the trench is filled with a trench dielectric material such that the common source/drain region is divided into electrically isolated first and second source/drain regions whereby the first transistor is electrically isolated from the second transistor.
摘要翻译：一种用于隔离半导体器件的方法，包括提供半导体衬底。半导体衬底包括横向移位的源极/漏极区域和沟道区域。第一和第二横向位移的MOS晶体管部分地形成在半导体衬底内。第一和第二晶体管具有公共源极/漏极区域。通过公共源极/漏极区形成隔离沟槽，并且沟槽填充有沟槽电介质材料，使得公共源极/漏极区域被分成电隔离的第一和第二源极/漏极区域，由此第一晶体管与第二晶体管。

26. 发明授权

US6117760A Method of making a high density interconnect formation 失效
标题翻译：制造高密度互连结构的方法
公开(公告)号：US6117760A
公开(公告)日：2000-09-12
申请号：US968682
申请日：1997-11-12
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Fred N. Hause
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Fred N. Hause
IPC分类号： H01L21/768 , H01L23/528 , H01L21/4763
CPC分类号： H01L21/76885 , H01L21/76838 , H01L23/5283 , H01L2924/0002
摘要： A technique is provided for forming interconnects laterally spaced from each other across a semiconductor topography by a deposited dielectric spacer layer. The lateral distance between each interconnect is advantageously dictated by the thickness of the spacer layer rather than by the minimum feature size of a lithographically patterned masking layer. In an embodiment, a first and second conductive interconnects are formed a spaced distance apart upon a semiconductor topography. The first and second interconnects are defined using optical lithography and an etch technique. A dielectric layer is CVD deposited across the exposed surfaces of the first and second interconnects and of the semiconductor topography. The CVD deposition conditions are controlled so as to form a relatively thin spacers laterally adjacent the sidewalls of the interconnects. A conductive material is then deposited across into a trench arranged between the first and second interconnects, and CMP polished such that the upper surface of the conductive material is at an elevational level proximate that of the surfaces of the interconnects. A third interconnect is thereby formed within the trench laterally adjacent the first and second interconnects.
摘要翻译：提供了一种技术，用于通过沉积的介电隔离层在半导体形貌上形成横向间隔开的互连。每个互连之间的横向距离有利地由隔离层的厚度而不是光刻图案化掩模层的最小特征尺寸决定。在一个实施例中，第一和第二导电互连在半导体形貌上分开形成间隔距离。第一和第二互连使用光刻和蚀刻技术来定义。介电层是跨越第一和第二互连的暴露表面和半导体形貌的CVD沉积的。控制CVD沉积条件以形成横向邻近互连侧壁的较薄的间隔件。然后将导电材料沉积到布置在第一和第二互连之间的沟槽中，并且CMP抛光，使得导电材料的上表面处于靠近互连表面的上表面。因此，在沟槽内形成第三互连件，横向地邻近第一和第二互连。

27. 发明授权

US6107129A Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance 失效
标题翻译：具有多个LDD和/或源极/漏极注入步骤以增强电路性能的集成电路
公开(公告)号：US6107129A
公开(公告)日：2000-08-22
申请号：US38511
申请日：1998-03-11
申请人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L29/78 , H01L29/72
CPC分类号： H01L29/6659 , H01L29/7833 , H01L29/7835
摘要： An integrated circuit is formed whereby MOS transistor junctions are produced which enhance the overall speed of the integrated circuit. The transistor junctions include multiple implants into the lightly doped drain (LDD) areas of the junction, the source/drain areas of the junction or both the LDD and source/drain areas. The first implant of the multiple implants serves to condition the implant area so that the second and subsequent implants are accurately placed with relatively high concentrations closely below the substrate surface. The resulting junction is therefore one which has relatively high drive strength, low contact resitivity, low source-to-drain parasitic resistance, and relatively low junction capacitance.
摘要翻译：形成集成电路，由此产生提高集成电路总体速度的MOS晶体管结。晶体管结包括多个注入到结点的轻掺杂漏极（LDD）区域，结点的源极/漏极区域以及LDD和源极/漏极区域两者。多个植入物的第一植入物用于调节植入区域，使得第二和随后的植入物以相对高的浓度精确地放置在基底表面附近。因此，所得到的结是具有相对高的驱动强度，低接触电阻率，低的源到漏寄生电阻和相对低的结电容的结。

28. 发明授权

US6090694A Local interconnect patterning and contact formation 失效
标题翻译：局部互连图案和接触形成
公开(公告)号：US6090694A
公开(公告)日：2000-07-18
申请号：US991742
申请日：1997-12-16
申请人： Fred N. Hause , Charles E. May , Mark I. Gardner
发明人： Fred N. Hause , Charles E. May , Mark I. Gardner
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76802 , H01L21/76832 , Y10S438/952
摘要： A method for forming a semiconductor device to produce a more distortion free via for interconnecting levels within a device or forming a connection between an external surface and an internal layer within a device includes the step of substituting a material similar to an etch stop adjacent one of the layers for the ARC. In other words, an etch stop is placed over the metal layer formed on a layer within the device. This is followed by a layer of silicon dioxide (SiO.sub.2) and then by a layer of material similar to the etch stop. Photoresist is placed on the layer of material similar to etch stop. The photoresist is exposed to light to form the location of the vias. The layer of material similar to etch stop, and the SiO.sub.2 layer are then removed in separate etching steps to form the via pathway from the resist to the etch stop adjacent the metal of the layer selected to be interconnected by the via. The resist can then be removed. This leaves the material similar to the etch stop located adjacent one surface of the SiO.sub.2 layer, and leaves the etch stop covering the metal in the via opening. One etch step can now be used to remove the etch stop covering the metal in the via opening and to remove the material similar to the etch stop located on the SiO.sub.2.
摘要翻译：用于形成半导体器件以产生用于在器件内互连电平或形成器件中的外表面和内部层之间的连接的无失真通孔的方法包括以下步骤：将与蚀刻停止相邻的材料 ARC的层。换句话说，蚀刻停止放置在形成在器件内的层上的金属层上。之后是二氧化硅层（SiO 2），然后是与蚀刻停止层相似的材料层。光刻胶放置在与蚀刻停止相似的材料层上。光致抗蚀剂暴露于光以形成通孔的位置。类似于蚀刻停止的材料层，然后在单独的蚀刻步骤中去除SiO 2层，以形成从抗蚀剂到蚀刻停止件的通孔路径，该蚀刻停止件邻近选定为由通孔相互连接的层的金属。然后可以除去抗蚀剂。这使得材料类似于位于SiO 2层的一个表面附近的蚀刻停止层，并且使蚀刻停止件覆盖通孔孔中的金属。现在可以使用一个蚀刻步骤去除覆盖通孔开口中的金属的蚀刻停止层，并且去除类似于位于SiO 2上的蚀刻停止层的材料。

29. 发明授权

US6049133A Semiconductor fabrication employing concurrent diffusion barrier and salicide formation 失效
标题翻译：采用同时扩散阻挡层和自对准硅化物形成的半导体制造
公开(公告)号：US6049133A
公开(公告)日：2000-04-11
申请号：US822121
申请日：1997-03-21
申请人： Fred N. Hause , Mark I. Gardner
发明人： Fred N. Hause , Mark I. Gardner
IPC分类号： H01C1/14 , H01C10/32 , H01C13/00 , H01C17/00 , H01L21/285 , H01L21/336 , H01L21/768 , H01L29/78
CPC分类号： H01L29/7833 , H01C10/32 , H01L21/28518 , H01L21/76841 , H01L21/76855 , H01L21/76856 , H01L29/665 , H01L29/6659
摘要： An integrated circuit fabrication process is provided in which a metal salicide and a diffusion barrier are formed concurrently. This process includes doping regions of a silicon substrate which are spaced apart by a polysilicon gate conductor, thereby forming source/drain junctions within the substrate upper surface. Oxide spacers are located on opposite sidewall surfaces of the gate conductor. The resulting semiconductor topography is then placed within a chamber having a pressurized and heated nitrogen ambient. A metal, i.e., titanium is deposited upon the semiconductor topography, and then annealing of the metal occurs. The titanium metal reacts with silicon at interfaces not containing nitrogen atoms, i.e., exclusive of the oxide spacers, to form titanium salicide. Concurrent with this reaction is the formation of titanium nitride upon the titanium metal. Finally, aluminum is deposited upon the titanium nitride to complete metallization. The titanium nitride diffusion barrier prevents aluminum spiking of the doped junctions below.
摘要翻译：提供了同时形成金属硅化物和扩散阻挡层的集成电路制造工艺。该工艺包括由多晶硅栅极导体隔开的硅衬底的掺杂区域，从而在衬底上表面内形成源极/漏极结。氧化物间隔物位于栅极导体的相对侧壁表面上。然后将所得半导体形貌放置在具有加压和加热的氮气环境的室内。在半导体形貌上沉积金属，即钛，然后发生金属的退火。钛金属在不含氮原子的界面（即不包括氧化物间隔物）与硅反应形成硅化硅。与此反应同时在钛金属上形成氮化钛。最后，铝沉积在氮化钛上以完成金属化。氮化钛扩散阻挡层阻止下述掺杂结的铝尖峰。

30. 发明授权

US5955785A Copper-containing plug for connection of semiconductor surface with overlying conductor 失效
标题翻译：用于将半导体表面与上覆导体连接的含铜插头
公开(公告)号：US5955785A
公开(公告)日：1999-09-21
申请号：US13762
申请日：1998-01-27
申请人： Mark I. Gardner , Fred N. Hause
发明人： Mark I. Gardner , Fred N. Hause
IPC分类号： H01L21/768 , H01L23/485 , H01L23/532 , H01L29/43
CPC分类号： H01L23/485 , H01L21/76838 , H01L23/53238 , H01L2924/0002 , Y10S257/915
摘要： An integrated circuit fabrication process is provided in which copper is used as the contact plug material for a via. The via is a hole etched through an interlevel dielectric which is disposed upon a semiconductor topography, e.g., a silicon-based substrate having junctions therein. An inert implant may form an implant region within the semiconductor topography lying underneath the via. The process for forming the copper plug involves depositing a diffusion barrier upon the interlevel dielectric and within the via. Copper is then deposited via chemical vapor deposition upon the diffusion barrier such that the copper fills the entire via and forms a layer above the via. The copper is etched from all areas except from within the via, thereby forming a copper plug in the via. The resulting surface is then subjected to chemical-mechanical polishing before the diffusion barrier is removed from areas exclusive of the via. A conductive layer can be placed upon the interlevel dielectric and the copper plug to form a contact between the conductive layer and the semiconductor topography.
摘要翻译：提供了一种集成电路制造工艺，其中使用铜作为通孔的接触插塞材料。通孔是通过层间电介质蚀刻的孔，其布置在半导体形貌上，例如其中具有结的硅基衬底。惰性植入物可以在位于通孔下方的半导体形貌内形成植入区域。形成铜插塞的过程包括在层间电介质和通孔内沉积扩散阻挡层。然后通过化学气相沉积将铜沉积在扩散阻挡层上，使得铜填充整个通孔并形成通孔上方的层。从除了通孔内的所有区域蚀刻铜，从而在通孔中形成铜塞。然后将所得表面进行化学机械抛光，然后从不包括通孔的区域除去扩散阻挡层。可以将导电层放置在层间电介质和铜插塞上以形成导电层和半导体形貌之间的接触。

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