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21. 发明申请

US20120056260A1 METHOD AND DEVICE EMPLOYING POLYSILICON SCALING 有权
标题翻译：使用聚硅氧烷尺寸的方法和装置
公开(公告)号：US20120056260A1
公开(公告)日：2012-03-08
申请号：US13294098
申请日：2011-11-10
申请人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L29/792
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

22. 发明授权

US07136306B2 Single bit nonvolatile memory cell and methods for programming and erasing thereof 失效
标题翻译：单位非易失性存储单元及其编程和擦除方法
公开(公告)号：US07136306B2
公开(公告)日：2006-11-14
申请号：US10680878
申请日：2003-10-07
申请人： Gang Xue , Jan Van Houdt
发明人： Gang Xue , Jan Van Houdt
IPC分类号： G11C16/04 , G11C5/06
CPC分类号： G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26
摘要： A method for programming a single bit nonvolatile memory cell integrated on a metal-dielectric-semiconductor technology chip. The memory cell comprises a semiconductor substrate including a source, a drain, and a channel in-between the source and the drain. The memory cell further comprises a control gate that comprises a gate electrode and a dielectric stack. The gate electrode is separated from the channel by the dielectric stack. Further, the dielectric stack comprises at least one charge storage dielectric layer. The method for programming the memory cell comprises applying electrical ground to the source, applying a first voltage having a first polarity to the drain, applying a second voltage of the first polarity to the control gate; and applying a third voltage having a second polarity opposite to the first polarity to the semiconductor substrate.
摘要翻译：一种用于编程集成在金属 - 电介质 - 半导体技术芯片上的单个位非易失性存储单元的方法。存储单元包括在源极和漏极之间包括源极，漏极和沟道的半导体衬底。该存储单元还包括一个包括栅电极和电介质叠层的控制栅极。栅极通过电介质堆叠与沟道分离。此外，电介质叠层包括至少一个电荷存储电介质层。用于对存储单元进行编程的方法包括将电接地施加到源极，向漏极施加具有第一极性的第一电压，将第一极性的第二电压施加到控制栅极; 以及将具有与所述第一极性相反的第二极性的第三电压施加到所述半导体衬底。

23. 发明授权

US06653682B1 Non-volatile electrically alterable semiconductor memory device 失效
标题翻译：非易失性电可变半导体存储器件
公开(公告)号：US06653682B1
公开(公告)日：2003-11-25
申请号：US09696616
申请日：2000-10-25
申请人： Jan Van Houdt , Gang Xue
发明人： Jan Van Houdt , Gang Xue
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , G11C16/0425 , H01L21/28273 , H01L29/42324 , H01L29/7886
摘要： Apparatus for an electrically programmable and erasable memory device and methods for programming, erasing and reading the device. The device has a single transistor including a source, a drain, a control gate and a floating gate positioned between the control gate, the source and the drain, where the floating gate is capacitively coupled to the drain. At least one part of the floating gate is partly positioned between the control gate, the drain and the source, and the other part of the floating gate overlaps with the drain. Further, the single transistor of the device includes means for injecting hot electrons generated by the drain induced secondary impact ionization onto the floating gate. Additionally, the means are arranged to induce Fowler-Nordheim tunnelling of charges from the floating gate to the drain.
摘要翻译：用于电可编程和可擦除存储器件的装置以及用于编程，擦除和读取器件的方法。器件具有单个晶体管，其包括位于控制栅极，源极和漏极之间的源极，漏极，控制栅极和浮置栅极，其中浮动栅极电容耦合到漏极。浮栅的至少一部分部分地位于控制栅极，漏极和源极之间，并且浮栅的另一部分与漏极重叠。此外，器件的单个晶体管包括用于将由漏极引起的次级冲击电离产生的热电子注入到浮动栅极上的装置。另外，这些装置被设置成将Fowler-Nordheim隧道从浮动栅极引导到漏极。

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