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21. 发明申请

US20060279988A1 System and method for matching resistance in a non-volatile memory 有权
标题翻译：用于在非易失性存储器中匹配电阻的系统和方法
公开(公告)号：US20060279988A1
公开(公告)日：2006-12-14
申请号：US11193924
申请日：2005-07-28
申请人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
发明人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
IPC分类号： G11C16/04
CPC分类号： G11C16/26
摘要： A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.
摘要翻译：用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。参考矩阵耦合到存储器矩阵并具有参考单元。逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。

22. 发明申请

US20060140030A1 System for performing fast testing during flash reference cell setting 有权
标题翻译：在闪存参考单元设置期间执行快速测试的系统
公开(公告)号：US20060140030A1
公开(公告)日：2006-06-29
申请号：US11089268
申请日：2005-03-24
申请人： Lorenzo Bedarida , Simone Bartoli , Stefano Surico , Massimiliano Frulio
发明人： Lorenzo Bedarida , Simone Bartoli , Stefano Surico , Massimiliano Frulio
IPC分类号： G11C29/00
CPC分类号： G11C29/028 , G11C16/04 , G11C29/24 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： An embedded circuit in a memory device is used in place of an external test device to perform time-consuming tasks such as voltage verification during the setting of reference cells. An external test device programs at least one reference cell to a predetermined value. The embedded circuit uses the cell programmed by the external device as a comparative reference to program additional reference cells.
摘要翻译：使用存储器件中的嵌入式电路来代替外部测试装置来执行耗费时间的任务，例如参考单元设置期间的电压验证。外部测试装置将至少一个参考单元编程为预定值。嵌入式电路使用由外部设备编程的单元作为比较参考来编程附加参考单元。

23. 发明授权

US07049880B2 High precision digital-to-analog converter with optimized power consumption 有权
标题翻译：具有优化功耗的高精度数模转换器
公开(公告)号：US07049880B2
公开(公告)日：2006-05-23
申请号：US11119675
申请日：2005-05-02
申请人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
发明人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/07 , H03M1/765
摘要： A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.
摘要翻译：一种具有双向切换装置的调节电荷泵电路，其在提供精确和稳定的电压输出的第一反馈通路与从电源提供具有低电流消耗的调节电压输出的第二反馈通路之间切换。第一反馈通道通过调节将电流吸引到电压输出的通过装置来保持精确的电压输出。第二反馈通道通过控制时钟输入到电荷泵的连接来调节电压输出。可变电阻用于设置电压输出的稳定电平。通过使用组合逻辑电路将数字输入信号转换成可变电阻器的控制信号，形成数模转换器。

24. 发明授权

US06567318B2 Control circuit for an output driving stage of an integrated circuit 有权
公开(公告)号：US06567318B2
公开(公告)日：2003-05-20
申请号：US09991493
申请日：2001-11-21
申请人： Lorenzo Bedarida , Luca Vandi , Carlo Lisi , Andrea Bellini
发明人： Lorenzo Bedarida , Luca Vandi , Carlo Lisi , Andrea Bellini
IPC分类号： G11C1604
CPC分类号： G05F3/245
摘要： An impedance control circuit controls the impedance of an integrated output driving stage. The integrated output driving stage includes at least one enabling/disabling transistor and at least one driving transistor. The impedance control circuit includes a variable impedance circuit having an impedance that varies with the temperature in correlation with the impedance of the output driving stage. A control circuit is connected to the variable impedance circuit for generating at least one enabling/disabling signal for the at least one enabling/disabling transistor based upon a control signal correlated to the impedance of the variable impedance circuit. The impedance control circuit also includes a current generating circuit for applying to the variable impedance circuit a current which remains substantially stable as the temperature varies.

25. 发明申请

US20080170455A1 Compensated current offset in a sensing circuit 有权
标题翻译：感测电路中的补偿电流偏移
公开(公告)号：US20080170455A1
公开(公告)日：2008-07-17
申请号：US11652742
申请日：2007-01-12
申请人： Lorenzo Bedarida , Gabriele Pelli , Simone Bartoli , Mauro Chinosi
发明人： Lorenzo Bedarida , Gabriele Pelli , Simone Bartoli , Mauro Chinosi
IPC分类号： G11C7/08
CPC分类号： G11C7/062 , G11C7/02 , G11C7/067 , G11C16/26 , G11C2207/063
摘要： A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.
摘要翻译：具有电流偏移功能的感测电路。在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。

26. 发明申请

US20080164948A1 BIASING CURRENT TO SPEED UP CURRENT MIRROR SETTLING TIME 有权
标题翻译：偏移电流以加快电流反射时间
公开(公告)号：US20080164948A1
公开(公告)日：2008-07-10
申请号：US11619729
申请日：2007-01-04
申请人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Andrea Bettini
发明人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Andrea Bettini
IPC分类号： H03F3/04
CPC分类号： H03F3/343 , G09G3/20 , G09G3/3216 , G09G3/3225
摘要： A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.
摘要翻译：电流镜电路包括耦合到第二电流镜晶体管的第一电流镜晶体管。负载耦合到第二电流镜晶体管。第一电流源耦合到第一电流镜晶体管以引起偏置电流流过第一电流镜晶体管，并且第二电流源耦合到第二电流镜晶体管并且与负载并联以分流偏置电流远离负载。

27. 发明授权

US07283396B2 System and method for matching resistance in a non-volatile memory 有权
标题翻译：用于在非易失性存储器中匹配电阻的系统和方法
公开(公告)号：US07283396B2
公开(公告)日：2007-10-16
申请号：US11193924
申请日：2005-07-28
申请人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
发明人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.
摘要翻译：用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。参考矩阵耦合到存储器矩阵并具有参考单元。逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。

28. 发明授权

US07130209B2 Flexible OTP sector protection architecture for flash memories 有权
标题翻译：灵活的OTP扇区保护架构，用于闪存
公开(公告)号：US07130209B2
公开(公告)日：2006-10-31
申请号：US11128648
申请日：2005-05-12
申请人： Riccardo Riva Reggiori , Lorenzo Bedarida , Giorgio Oddone , Fabio Tassan Caser
发明人： Riccardo Riva Reggiori , Lorenzo Bedarida , Giorgio Oddone , Fabio Tassan Caser
IPC分类号： G11C17/00
CPC分类号： G11C16/22 , G11C2216/26
摘要： A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds to a portion of a block of the plurality of blocks. The OTP cell allows modification of the portion of the block when the OTP cell is in a first state and permanently prevents modification of the portion of the block when the OTP cell is in a second state. The OTP cell logic uses the plurality of OTP cells to select the portion of the block as corresponding to the OTP cell. This portion of the block is write protected when the OTP cell is placed in the second state.
摘要翻译：公开了一种用于保护具有多个块的存储器不被修改的方法和系统。该方法和系统包括提供与OTP单元耦合的多个一次可编程（OTP）单元和OTP单元逻辑。多个OTP单元的OTP单元对应于多个块的块的一部分。当OTP小区处于第一状态时，OTP小区允许修改块的部分，并且当OTP小区处于第二状态时永久地防止修改块的部分。 OTP单元逻辑使用多个OTP单元来选择与OTP单元相对应的块的该部分。当OTP单元处于第二状态时，块的这一部分是写保护的。

29. 发明申请

US20050189983A1 High precision digital-to-analog converter with optimized power consumption 有权
公开(公告)号：US20050189983A1
公开(公告)日：2005-09-01
申请号：US11119675
申请日：2005-05-02
申请人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
发明人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
IPC分类号： G05F1/10 , G05F3/02 , H02M20060101 , H02M3/07 , H02M5/42 , H03M1/76
CPC分类号： H02M3/07 , H03M1/765
摘要： A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.

30. 发明授权

US06854040B1 Non-volatile memory device with burst mode reading and corresponding reading method 有权
标题翻译：具有突发模式读取的非易失性存储器件和相应的读取方法
公开(公告)号：US06854040B1
公开(公告)日：2005-02-08
申请号：US09717938
申请日：2000-11-21
申请人： Simone Bartoli , Antonino Geraci , Mauro Sali , Lorenzo Bedarida
发明人： Simone Bartoli , Antonino Geraci , Mauro Sali , Lorenzo Bedarida
IPC分类号： G11C7/10 , G06F12/00 , G06F13/28 , G11C8/04
CPC分类号： G11C7/1072 , G11C7/1033 , G11C7/1045
摘要： A read control circuit and a reading method for an electronic memory device integrated on a semiconductor includes a non-volatile memory matrix with associated row and column decoders connected to respective outputs of an address counter. An address transition detect (ATD) circuit detects an input transition as the memory device is being accessed, and read amplifiers and attendant registers transfer the data read from the memory matrix to the output. The read control circuit includes a detection circuit to which is input a clock signal and a logic signal to enable reading in the burst mode. A burst read mode control logic circuit is connected downstream of the detection circuit. The method includes accessing the memory matrix in a random read mode, detecting a request for access in the burst read mode, and executing the parallel reading of a plurality of memory words during a single period of time clocked by the clock signal.
摘要翻译：集成在半导体上的电子存储装置的读取控制电路和读取方法包括具有连接到地址计数器的相应输出的相关联的行和列解码器的非易失性存储器矩阵。地址转换检测（ATD）电路在正在访问存储器件时检测输入转换，并且读取放大器和伴随寄存器将从存储器矩阵读取的数据传送到输出。读取控制电路包括检测电路，在该检测电路中输入时钟信号和逻辑信号，使得能够以突发模式进行读取。突发读模式控制逻辑电路连接在检测电路的下游。该方法包括以随机读取模式访问存储器矩阵，以突发读取模式检测访问请求，以及在由时钟信号计时的单个时间段内执行多个存储器字的并行读取。

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