专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07868374B2 Semitubular metal-oxide-semiconductor field effect transistor 有权
标题翻译：半金属氧化物半导体场效应晶体管
公开(公告)号：US07868374B2
公开(公告)日：2011-01-11
申请号：US12034899
申请日：2008-02-21
申请人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Jack A. Mandelman
发明人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Jack A. Mandelman
IPC分类号： H01L29/788
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/10826 , H01L29/66795 , H01L29/7841 , H01L29/7853
摘要： An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure in a three-walled configuration is formed. A semitubular field effect transistor comprising inner and outer gate dielectric layers, an inner gate electrode, an outer gate electrode, and source and drain regions is formed on the semitubular epitaxial semiconductor structure. The semitubular field effect transistor may operate as an SOI transistor with a tighter channel control through the inner and outer gate electrodes, or as a memory device storing electrical charges in the body region within the semitubular epitaxial semiconductor structure.
摘要翻译：在衬底上的多孔硅部分的外侧壁上形成硅锗合金层和外延应变硅层的外延半导体层或叠层。去除多孔硅部分和任何硅锗合金材料，并形成三壁结构的半管状外延半导体结构。在半管外延半导体结构上形成包括内栅电介质层和外栅电介质层，内栅电极，外栅电极以及源极和漏极区的半管场效应晶体管。半管场效应晶体管可以作为具有通过内部和外部栅极电极的更严格的沟道控制的SOI晶体管，或作为在半管外延半导体结构内的体区中存储电荷的存储器件。

22. 发明申请

US20100052034A1 FLASH MEMORY GATE STRUCTURE FOR WIDENED LITHOGRAPHY WINDOW 失效
标题翻译：闪存光栅窗口的闪存存储器门结构
公开(公告)号：US20100052034A1
公开(公告)日：2010-03-04
申请号：US12198345
申请日：2008-08-26
申请人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu
发明人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/7881 , H01L29/66825
摘要： A first portion of a semiconductor substrate belonging to a flash memory device region is recessed to a recess depth to form a recessed region, while a second portion of the semiconductor substrate belonging to a logic device region is protected with a masking layer. A first gate dielectric layer and a first gate conductor layer formed within the recessed region such that the first gate conductive layer is substantially coplanar with the top surfaces of the shallow trench isolation structures. A second gate dielectric layer, a second gate conductor layer, and a gate cap hard mask layer, each having a planar top surface, is subsequently patterned. The pattern of the gate structure in the flash memory device region is transferred into the first gate conductor layer and the first gate dielectric layer to form a floating gate and a first gate dielectric, respectively.
摘要翻译：属于闪存器件区域的半导体衬底的第一部分凹陷到凹陷深度以形成凹陷区域，而属于逻辑器件区域的半导体衬底的第二部分被掩蔽层保护。形成在凹陷区域内的第一栅介质层和第一栅极导体层，使得第一栅极导电层与浅沟槽隔离结构的顶表面基本共面。随后对第二栅介质层，第二栅极导体层和栅帽硬掩模层进行构图，每个具有平坦的顶表面。闪存器件区域中的栅极结构的图案被转移到第一栅极导体层和第一栅极介电层中，以分别形成浮置栅极和第一栅极电介质。

23. 发明申请

US20090305493A1 ADOPTING FEATURE OF BURIED ELECTRICALLY CONDUCTIVE LAYER IN DIELECTRICS FOR ELECTRICAL ANTI-FUSE APPLICATION 有权
标题翻译：采用电抗电阻应用电路的电导电导体层的特征
公开(公告)号：US20090305493A1
公开(公告)日：2009-12-10
申请号：US12541502
申请日：2009-08-14
申请人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Nicholas C. Fuller , Louis C. Hsu
发明人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Nicholas C. Fuller , Louis C. Hsu
IPC分类号： H01L21/768
CPC分类号： H01L23/5252 , H01L21/76843 , H01L21/76844 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
摘要翻译：提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。也可以通过增加局部温度来加速相邻互连之间的电阻的降低。

24. 发明授权

US07563710B2 Method of fabrication of interconnect structures 失效
标题翻译：互连结构的制造方法
公开(公告)号：US07563710B2
公开(公告)日：2009-07-21
申请号：US11860602
申请日：2007-09-25
申请人： Chih-Chao Yang , Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Meeyoung H. Yoon
发明人： Chih-Chao Yang , Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Meeyoung H. Yoon
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a damascene wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor.
摘要翻译：一种形成镶嵌线的方法。该方法包括：在电介质层的顶表面上形成掩模层; 在掩模层中形成开口; 在电介质层中形成沟槽，其中电介质层不被掩模层保护; 使掩模层下方的沟槽的侧壁凹陷; 在沟槽和掩模层的所有暴露表面上形成共形导电衬垫; 用芯电导体填充沟槽; 去除在电介质层的顶表面上方延伸的导电衬垫的部分，并去除掩模层; 以及在所述芯导体的顶表面上形成导电帽。

25. 发明申请

US20090117360A1 SELF-ASSEMBLED MATERIAL PATTERN TRANSFER CONTRAST ENHANCEMENT 审中-公开
标题翻译：自组装材料模式转移对比增强
公开(公告)号：US20090117360A1
公开(公告)日：2009-05-07
申请号：US11933760
申请日：2007-11-01
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Habib Hichri , Louis L. Hsu , Kaushik A. Kumar , Carl Radens , Shahab Siddiqui , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Habib Hichri , Louis L. Hsu , Kaushik A. Kumar , Carl Radens , Shahab Siddiqui , Chih-Chao Yang
IPC分类号： G03C1/73 , B05D3/00 , B32B27/06
CPC分类号： H01L21/0337 , B81C1/00031 , B81C2201/0149 , B82Y30/00 , H01L21/0338
摘要： A non-photosensitive polymeric resist containing at least two immiscible polymeric block components is deposited on the planar surface. The non-photosensitive polymeric resist is annealed to allow phase separation of immiscible components and developed to remove at least one of the at least two polymeric block components. Nanoscale features, i.e., features of nanometer scale, including at least one recessed region having a nanoscale dimension is formed in the polymeric resist. The top surface of the polymeric resist is modified for enhanced etch resistance by an exposure to an energetic beam, which allows the top surface of the patterned polymeric resist to become more resistant to etching processes and chemistries. The enhanced ratio of etch resistance between the two types of surfaces provides improved image contrast and fidelity between areas having the top surface and the at least one recessed region.
摘要翻译：含有至少两个不混溶的聚合物嵌段组分的非光敏聚合物抗蚀剂沉积在平面上。将非光敏聚合物抗蚀剂退火以允许不相容组分的相分离并显影以除去至少两种聚合物嵌段组分中的至少一种。在聚合物抗蚀剂中形成纳米尺度特征，即纳米尺度的特征，包括具有纳米级尺寸的至少一个凹陷区域。聚合物抗蚀剂的顶表面通过暴露于能量束而被改进以提高耐蚀刻性，这允许图案化聚合物抗蚀剂的顶表面变得更耐蚀刻工艺和化学物质。两种类型表面之间的增强的耐蚀刻比提供了改善的图像对比度和具有顶表面和至少一个凹陷区域的区域之间的保真度。

26. 发明授权

US07514271B2 Method of forming high density planar magnetic domain wall memory 有权
标题翻译：形成高密度平面磁畴壁记忆的方法
公开(公告)号：US07514271B2
公开(公告)日：2009-04-07
申请号：US11694183
申请日：2007-03-30
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/00 , G11C5/12 , G11C11/14
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A method of forming a magnetic domain wall memory apparatus with write/read capability includes forming a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location: forming a magnetic read element associated with each of the shift register structures: and forming a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of one of the plurality of discontinuities in the associated shift register structure.
摘要翻译：形成具有写入/读取能力的磁畴壁存储装置的方法包括形成多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个其中的不连续性以便于域壁位置：形成与每个移位寄存器结构相关联的磁读取元件;以及形成与每个移位寄存器结构相关联的磁写元件，所述磁写入元件还包括具有收缩的写入线其中，所述收缩部位于与相关联的移位寄存器结构中的所述多个不连续之一的位置相对应的点处。

27. 发明申请

US20080283964A1 ADOPTING FEATURE OF BURIED ELECTRICALLY CONDUCTIVE LAYER IN DIELECTRICS FOR ELECTRICAL ANTI-FUSE APPLICATION 有权
标题翻译：采用电抗电阻应用电路的电导电导体层的特征
公开(公告)号：US20080283964A1
公开(公告)日：2008-11-20
申请号：US12144229
申请日：2008-06-23
申请人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Nicholas C. Fuller , Louis C. Hsu
发明人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Nicholas C. Fuller , Louis C. Hsu
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5252 , H01L21/76843 , H01L21/76844 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
摘要翻译：提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。也可以通过增加局部温度来加速相邻互连之间的电阻的降低。

28. 发明授权

US07223691B2 Method of forming low resistance and reliable via in inter-level dielectric interconnect 有权
标题翻译：在层间电介质互连中形成低电阻和可靠通孔的方法
公开(公告)号：US07223691B2
公开(公告)日：2007-05-29
申请号：US10965031
申请日：2004-10-14
申请人： Cyril Cabral, Jr. , Lawrence A. Clevenger , Timothy J. Dalton , Patrick W. DeHaven , Chester T. Dziobkowski , Sunfei Fang , Terry A. Spooner , Tsong-Lin L. Tai , Kwong Hon Wong , Chin-Chao Yang
发明人： Cyril Cabral, Jr. , Lawrence A. Clevenger , Timothy J. Dalton , Patrick W. DeHaven , Chester T. Dziobkowski , Sunfei Fang , Terry A. Spooner , Tsong-Lin L. Tai , Kwong Hon Wong , Chin-Chao Yang
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76888
摘要： A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.
摘要翻译：具有低接触电阻和改进的可靠性的新颖的层间接触通孔结构以及形成接触通孔的方法。该方法包括以下步骤：通过层间电介质层蚀刻开口以暴露下面的金属（铜）层表面; 并且将惰性气体（氮气）的低能量离子注入进入下面暴露的金属; 并且将耐火衬垫沉积到壁和底部通孔结构中，由于进行的惰性气体注入的存在而将具有较低的接触电阻。优选地，惰性氮气与下面暴露的铜金属反应形成一层薄的CuN。

29. 发明授权

US07001835B2 Crystallographic modification of hard mask properties 失效
标题翻译：硬掩模性能的晶体学修饰
公开(公告)号：US07001835B2
公开(公告)日：2006-02-21
申请号：US10707119
申请日：2003-11-21
申请人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Kaushik A. Kumar , Stephen M. Rossnagel , Andrew H. Simon , Douglas C. La Tulipe, Jr.
发明人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Kaushik A. Kumar , Stephen M. Rossnagel , Andrew H. Simon , Douglas C. La Tulipe, Jr.
IPC分类号： H01L21/4763
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/0332 , H01L21/0337 , H01L21/2855 , H01L21/76841 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 μOhm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N2 and a flow rate such that (N2 flow)/(N2+carrier flow)>0.5.
摘要翻译：集成电路后端的硬掩模层由具有小于50％Ta且电阻率大于400μΩ-cm的组成的TaN形成，使得其在可见光中基本上是透明的并且允许上和通过硬掩模和ILD的中间层降低对准标记。形成硬掩模的优选方法是通过在含有N 2 O 2的环境中溅射沉积Ta并使流速使得（N 2 N 2 O 2）/（N _{2 +载体流）> 0.5。}

30. 发明授权

US08486512B2 Pattern formation employing self-assembled material 有权
公开(公告)号：US08486512B2
公开(公告)日：2013-07-16
申请号：US13430179
申请日：2012-03-26
申请人： Charles T. Black , Timothy J. Dalton , Bruce B. Doris , Carl J. Radens
发明人： Charles T. Black , Timothy J. Dalton , Bruce B. Doris , Carl J. Radens
IPC分类号： B32B3/00
CPC分类号： H01L21/0338 , B81B2203/0369 , B81C1/00031 , B81C2201/0149 , B81C2201/0198 , B82Y30/00 , H01L21/0337 , H01L51/0017 , Y10S977/882 , Y10S977/887 , Y10S977/888 , Y10T428/24479 , Y10T428/2457 , Y10T428/24612 , Y10T428/24736 , Y10T428/24802
摘要： In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ⅓ of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式