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21. 发明授权

US06777774B2 Low noise inductor using electrically floating high resistive and grounded low resistive patterned shield 有权
标题翻译：低噪声电感使用电浮动高电阻和接地的低电阻图案屏蔽
公开(公告)号：US06777774B2
公开(公告)日：2004-08-17
申请号：US10125244
申请日：2002-04-17
申请人： Sia Choon Beng , Yeo Kiat Seng , Sanford Chu , Lap Chan , Chew Kok-Wai
发明人： Sia Choon Beng , Yeo Kiat Seng , Sanford Chu , Lap Chan , Chew Kok-Wai
IPC分类号： H01L2900
CPC分类号： H01L28/10 , H01L23/552 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： A novel complimentary shielded inductor on a semiconductor is disclosed. A region of electrically floating high resistive material is deposited between the inductor and the semiconductor substrate. The high resistive shield is patterned with a number of gaps, such that a current induced in the shield by the inductor does not have a closed loop path. The high resistive floating shield compliments a grounded low resistive shield to achieve higher performance inductors. In this fashion, noise in the substrate is reduced. The novel complimentary shield does not significantly degrade the figures of merit of the inductor, such as, quality factor and resonance frequency. In one embodiment, the grounded shield is made of patterned N-well (or P-well) structures. In still another embodiment, the low resistive electrically grounded shield is made of patterned Silicide, which may be formed on portions of the substrate itself.
摘要翻译：公开了一种半导体上的新型有用屏蔽电感器。电浮动高电阻材料的区域沉积在电感器和半导体衬底之间。高电阻屏蔽层被图案化为多个间隙，使得由电感器在屏蔽层中感应的电流不具有闭环路径。高电阻浮动屏蔽补充了接地的低电阻屏蔽以实现更高性能的电感器。以这种方式，衬底中的噪声降低。新型互补屏蔽不会显着降低电感器的品质因数，如品质因数和谐振频率。在一个实施例中，接地屏蔽由图案化的N阱（或P阱）结构制成。在另一个实施例中，低电阻电接地屏蔽由图案化的硅化物制成，其可以形成在衬底本身的部分上。

22. 发明授权

US08324031B2 Diffusion barrier and method of formation thereof 有权
标题翻译：扩散屏障及其形成方法
公开(公告)号：US08324031B2
公开(公告)日：2012-12-04
申请号：US12144652
申请日：2008-06-24
申请人： Shyue Seng Tan , Lee Wee Teo , Yung Fu Chong , Elgin Quek , Sanford Chu
发明人： Shyue Seng Tan , Lee Wee Teo , Yung Fu Chong , Elgin Quek , Sanford Chu
IPC分类号： H01L21/00
CPC分类号： H01L29/66537 , H01L21/26506 , H01L21/266 , H01L21/3223 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823871 , H01L21/823878 , H01L23/532 , H01L27/088 , H01L29/0649 , H01L29/1083 , H01L29/32 , H01L29/36 , H01L29/66477 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.
摘要翻译：提出了一种形成装置的方法。该方法包括提供具有第一和第二区域的结构。在第一和第二区域的至少一部分之间形成扩散阻挡层。扩散屏障包括减少元件在第一和第二区域之间的扩散的空腔。

23. 发明申请

US20120119293A1 HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER 有权
标题翻译：具有增强型电介质层的高性能LDMOS器件
公开(公告)号：US20120119293A1
公开(公告)日：2012-05-17
申请号：US13333118
申请日：2011-12-21
申请人： Sanford Chu , Yisuo Li , Guowei Zhang , Verma Purakh
发明人： Sanford Chu , Yisuo Li , Guowei Zhang , Verma Purakh
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0847 , H01L29/66659 , H01L29/7846
摘要： An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region.
摘要翻译： LDMOS器件包括具有表面的衬底和覆盖该表面的栅电极，并且在栅电极下方的衬底中限定沟道区。漏极区域与沟道区域隔开隔离区域。隔离区域包括高拉伸应力的区域，并且被配置为在靠近漏极区域的基板中引起局部应力。隔离区域中的高拉伸应力的区域可以由高应力氧化硅或高应力氮化硅形成。在优选实施例中，隔离区是形成在栅极电极和漏极区域中间的衬底中的浅沟槽隔离区。

24. 发明授权

US08163621B2 High performance LDMOS device having enhanced dielectric strain layer 有权
公开(公告)号：US08163621B2
公开(公告)日：2012-04-24
申请号：US12134860
申请日：2008-06-06
申请人： Sanford Chu , Yisuo Li , Guowei Zhang , Verma Purakh
发明人： Sanford Chu , Yisuo Li , Guowei Zhang , Verma Purakh
IPC分类号： H01L21/336
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0847 , H01L29/66659 , H01L29/7846
摘要： An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region.

25. 发明授权

US07867862B2 Semiconductor structure including high voltage device 有权
标题翻译：半导体结构包括高压器件
公开(公告)号：US07867862B2
公开(公告)日：2011-01-11
申请号：US11855168
申请日：2007-09-14
申请人： Jeoung Mo Koo , Purakh Raj Verma , Sanford Chu , Chunlin Zhu , Yisuo Li
发明人： Jeoung Mo Koo , Purakh Raj Verma , Sanford Chu , Chunlin Zhu , Yisuo Li
IPC分类号： H01L21/335
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/105 , H01L29/66568 , H01L29/7833
摘要： A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure.
摘要翻译：高压器件包括其上限定有器件区域的衬底。栅极堆叠设置在器件区域中的衬底上。沟道区域位于栅堆叠下方的衬底中，而第一扩散区位于栅层叠的第一侧上的衬底中。位于栅极堆叠的第一侧的衬底中的第一隔离结构分离通道和第一扩散区域。高电压装置还包括在衬底中的第一漂移区域，其将沟道耦合到第一扩散区域，其中第一漂移区域包括符合第一隔离结构的轮廓的不均匀的深度分布。

26. 发明授权

US06714112B2 Silicon-based inductor with varying metal-to-metal conductor spacing 失效
标题翻译：具有不同金属 - 金属导体间距的硅基电感器
公开(公告)号：US06714112B2
公开(公告)日：2004-03-30
申请号：US10144542
申请日：2002-05-10
申请人： Sia Choon Beng , Yeo Kiat Seng , Sanford Chu
发明人： Sia Choon Beng , Yeo Kiat Seng , Sanford Chu
IPC分类号： H01F500
CPC分类号： H01F17/0006 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A silicon-based inductor in a semiconductor is disclosed. One embodiment provides for an inductor having a metal region comprising turns. The metal region has spacing between adjacent turns. The width of the spacing varies. The spacing is pre-determined to optimize the performance of the inductor by reducing eddy currents in the turns and reducing eddy currents induced in a substrate. One embodiment provides for an inductor having a spiral structure. The spiral structure may have a number of turns with the spacing between the turns of the inductor being larger near the inside of the spiral structure. A large spacing between the inductor's inner turns may serve to reduce both conductor eddy currents and the induced substrate current. Thus, the structure improves the inductor's overall performance.
摘要翻译：公开了半导体中的硅基电感器。一个实施例提供了具有包括匝的金属区域的电感器。金属区域在相邻的匝之间具有间隔。间距的宽度变化。通过减小匝中的涡电流并减少在衬底中感应的涡电流，预先确定间距以优化电感器的性能。一个实施例提供具有螺旋结构的电感器。螺旋结构可以具有多个匝数，在螺旋结构的内部附近，电感器匝之间的间距更大。电感器内圈之间的大间距可用于减少导体涡流和感应衬底电流。因此，该结构提高了电感器的整体性能。

27. 发明授权

US06576526B2 Darc layer for MIM process integration 有权
标题翻译：用于MIM工艺集成的Darc层
公开(公告)号：US06576526B2
公开(公告)日：2003-06-10
申请号：US09900398
申请日：2001-07-09
申请人： Shao Kai , Wu-Guan Ping , Chen Liang , Cheng-Wei Hua , Sanford Chu , Daniel Yen
发明人： Shao Kai , Wu-Guan Ping , Chen Liang , Cheng-Wei Hua , Sanford Chu , Daniel Yen
IPC分类号： H01L2120
CPC分类号： H01L28/55 , H01L21/31122 , H01L21/32136
摘要： A new processing sequence is provided for the creation of a MIM capacitor. The process starts with the deposition of a first layer of metal. Next are deposited listed, a thin layer of metal, a layer of insulation, a second layer of metal and a layer of Anti Reflective Coating. An etch is then performed to form the second electrode of the MIM capacitor (using the etch stop layer to stop this etch), MIM spacers are formed on the sidewalls of the second electrode of the MIM capacitor (also using the etch stop layer to stop this etch). The dielectric and first electrode of the MIM capacitor are formed by etching through the second layer of insulation and the first layer of metal. This is followed by conventional processing to create contact points to the MIM capacitor.
摘要翻译：为MIM电容器的创建提供了新的处理顺序。该过程开始于沉积第一层金属。接下来是沉积列表，薄层金属，一层绝缘层，第二层金属和一层抗反射涂层。然后进行蚀刻以形成MIM电容器的第二电极（使用蚀刻停止层来停止该蚀刻），MIM间隔物形成在MIM电容器的第二电极的侧壁上（也使用蚀刻停止层停止这个蚀刻）。 MIM电容器的电介质和第一电极通过蚀刻穿过第二绝缘层和第一金属层而形成。接下来是常规处理以产生与MIM电容器的接触点。

28. 发明授权

US09029227B2 P-channel flash with enhanced band-to-band tunneling hot electron injection 有权
标题翻译： P通道闪存具有增强的带对带隧道热电子注入
公开(公告)号：US09029227B2
公开(公告)日：2015-05-12
申请号：US13038081
申请日：2011-03-01
申请人： Eng Huat Toh , Elgin Quek , Ying Keung Leung , Sanford Chu
发明人： Eng Huat Toh , Elgin Quek , Ying Keung Leung , Sanford Chu
IPC分类号： H01L21/336 , H01L21/02 , H01L27/06 , H01L29/792 , H01L21/28 , H01L29/51
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/513
摘要： A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a substrate, forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack, forming spacers on the layer, forming raised source/drains, removing the dummy gate stack, forming a cavity between the spacers, and forming a memory gate stack in the cavity. Different embodiments include forming the layer of a narrow bandgap material, a narrow bandgap layer under the spacers and a wide bandgap layer adjacent thereto, or a wide bandgap layer under the spacers, a narrow bandgap layer adjacent thereto, and a wide bandgap layer on the narrow bandgap layer.
摘要翻译：形成p沟道闪速存储器，其中嵌入有形成有升高的源极/漏极的异质结层中的电荷存储堆叠。实施例包括在衬底上形成虚拟栅极堆叠，通过选择性外延生长在虚设栅极堆叠的每一侧上在衬底上形成层，在层上形成间隔物，形成升高的源极/漏极，去除虚拟栅极堆叠，形成间隔件之间的空腔，并且在空腔中形成存储器栅极堆叠。不同的实施例包括形成窄带隙材料的层，在间隔物下方的窄带隙层和与其相邻的宽带隙层，或在间隔物下方的宽带隙层，与其相邻的窄带隙层，以及宽带隙层窄带隙层。

29. 发明授权

US09006055B2 High voltage FINFET structure 有权
标题翻译：高电压FINFET结构
公开(公告)号：US09006055B2
公开(公告)日：2015-04-14
申请号：US13754065
申请日：2013-01-30
申请人： Han Xiao , Shaoqiang Zhang , Sanford Chu , Liming Li
发明人： Han Xiao , Shaoqiang Zhang , Sanford Chu , Liming Li
IPC分类号： H01L21/00 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/785 , H01L29/7855
摘要： Methods for forming FIN-shaped field effect transistors (FINFETs) capable of withstanding high voltage applications and the resulting devices are disclosed. Embodiments include forming a source and a drain on a substrate, forming a thin body (FIN) on the substrate and connecting the source and the drain, forming a gate over top and side surfaces of a first part of the FIN, thereby defining a drain-side FIN region of the FIN between the gate and the drain, and forming a shielding region over top and side surfaces of a second part of the FIN in the drain-side FIN region.
摘要翻译：公开了能够承受高电压应用的FIN形状场效应晶体管（FINFET）和所得到的器件的方法。实施例包括在衬底上形成源极和漏极，在衬底上形成薄体（FIN）并连接源极和漏极，在FIN的第一部分的顶部和侧面上形成栅极，由此限定漏极在栅极和漏极之间的FIN的FIN边缘区域，并且在漏极侧FIN区域中在FIN的第二部分的顶表面和侧表面上形成屏蔽区域。

30. 发明授权

US08293614B2 High performance LDMOS device having enhanced dielectric strain layer 有权
标题翻译：具有增强的介电应变层的高性能LDMOS器件
公开(公告)号：US08293614B2
公开(公告)日：2012-10-23
申请号：US13333118
申请日：2011-12-21
申请人： Sanford Chu , Yisuo Li , Guowei Zhang , Verma Purakh
发明人： Sanford Chu , Yisuo Li , Guowei Zhang , Verma Purakh
IPC分类号： H01L29/66
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0847 , H01L29/66659 , H01L29/7846
摘要： An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region.
摘要翻译： LDMOS器件包括具有表面的衬底和覆盖该表面的栅电极，并且在栅电极下方的衬底中限定沟道区。漏极区域与沟道区域隔开隔离区域。隔离区域包括高拉伸应力的区域，并且被配置为在靠近漏极区域的基板中引起局部应力。隔离区域中的高拉伸应力的区域可以由高应力氧化硅或高应力氮化硅形成。在优选实施例中，隔离区是形成在栅极电极和漏极区域中间的衬底中的浅沟槽隔离区。

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