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21. 发明授权

US07122439B2 Method of fabricating a bottle trench and a bottle trench capacitor 有权
标题翻译：制造瓶沟槽和瓶槽电容器的方法
公开(公告)号：US07122439B2
公开(公告)日：2006-10-17
申请号：US10904582
申请日：2004-11-17
申请人： Oh-Jung Kwon , Kenneth T. Settlemyer, Jr. , Ravikumar Ramachandran , Min-Soo Kim
发明人： Oh-Jung Kwon , Kenneth T. Settlemyer, Jr. , Ravikumar Ramachandran , Min-Soo Kim
IPC分类号： H01L21/20
CPC分类号： H01L27/1087 , H01L29/66181
摘要： A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench.
摘要翻译：制造瓶沟槽和瓶沟电容器的方法。该方法包括：提供衬底; 在所述衬底中形成沟槽，所述沟槽具有侧壁和底部，所述沟槽具有与所述衬底的顶表面相邻的上部区域和与所述沟槽的底部相邻的下部区域; 在沟槽的底部区域形成衬底的氧化层; 并且从沟槽的底部区域去除衬底的氧化层，沟槽的下部区域的横截面面积大于沟槽的上部区域的横截面面积。

22. 发明授权

US07122437B2 Deep trench capacitor with buried plate electrode and isolation collar 有权
标题翻译：深沟槽电容器，埋置电极和隔离环
公开(公告)号：US07122437B2
公开(公告)日：2006-10-17
申请号：US10741203
申请日：2003-12-19
申请人： Thomas W. Dyer , Chun-yung Sung , Ravikumar Ramachandran , Ramachandra Divakaruni , Carl Radens
发明人： Thomas W. Dyer , Chun-yung Sung , Ravikumar Ramachandran , Ramachandra Divakaruni , Carl Radens
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L29/945
摘要： A deep trench capacitor used in a trench DRAM includes a buried plate and an isolation collar. The deep trench is bottle-shaped, and the isolation collar is formed in upper portion of the wider region of the bottle-shaped trench. The buried plate surrounds the lower portion of the wider part of the bottle-shaped trench, and hemispherical grain polysilicon lines the walls of at least the lower portion of the wider part of the trench. A nitride liner layer lines the inner walls of the oxide collar and prevents diffusion of dopant through the oxide collar into the substrate when the HSG polysilicon and the doped buried plate are formed. The buried plate region is self-aligned to the isolation collar. The depth of the top of the wider part of the bottle shape and the bottom depth of the isolation collar are determined by successive resist deposition and recessing steps.
摘要翻译：在沟槽DRAM中使用的深沟槽电容器包括掩埋板和隔离环。深沟是瓶形的，并且隔离套环形成在瓶形沟槽的较宽区域的上部。掩埋板围绕瓶形沟槽的较宽部分的下部，半球状晶粒多晶硅线路至少沟槽较宽部分的下部的壁。当形成HSG多晶硅和掺杂掩埋板时，氮化物衬垫层线化氧化物环的内壁并防止掺杂剂通过氧化物环到衬底中的扩散。掩埋板区域与隔离套环自对准。通过连续的抗蚀剂沉积和凹陷步骤确定瓶子形状的较宽部分的顶部的深度和隔离环的底部深度。

23. 发明申请

US20050287823A1 DUAL-FREQUENCY SILICON NITRIDE FOR SPACER APPLICATION 失效
标题翻译：双频氮化硅适用于间距应用
公开(公告)号：US20050287823A1
公开(公告)日：2005-12-29
申请号：US10710257
申请日：2004-06-29
申请人： Ravikumar Ramachandran , James Kelliher , Shreesh Narasimha , Jeffrey Sleight
发明人： Ravikumar Ramachandran , James Kelliher , Shreesh Narasimha , Jeffrey Sleight
IPC分类号： H01L21/31 , H01L21/318 , H01L21/44 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/3185 , H01L21/0217 , H01L21/02274 , H01L21/823864
摘要： A silicon nitride spacer material for use in forming a PFET device and a method for making the spacer includes the use of a dual-frequency plasma enhanced CVD process wherein the temperature is in the range depositing a silicon nitride layer by means of a low-temperature dual-frequency plasma enhanced CVD process, at a temperature in the range 400° C. to 550° C. The process pressure is in the range 2 Torr to 5 Torr. The low frequency power is in the range 0 W to 50 W, and the high frequency power is in the range 90 W to 110 W. The precursor gases of silane, ammonia and nitrogen flow at flow rates in the ratio 240:3200:4000 sccm. The use of the silicon nitride spacer of the invention to form a PFET device having a dual spacer results in a 10%-15% performance improvement compared to a similar PFET device having a silicon nitride spacer formed by a RTCVD process.
摘要翻译：用于形成PFET器件的氮化硅间隔物材料和用于制造间隔物的方法包括使用双频等离子体增强CVD工艺，其中温度在通过低温下沉积氮化硅层的范围双频等离子体增强CVD工艺，温度范围为400°C至550°C。工艺压力范围为2 Torr至5 Torr。低频功率在0W至50W的范围内，高频功率在90W至110W的范围内。硅烷，氨和氮气的前体气体以240：3200：4000的比例流动 sccm。与具有通过RTCVD工艺形成的氮化硅间隔物的类似PFET器件相比，使用本发明的氮化硅间隔物形成具有双间隔物的PFET器件导致10％-15％的性能提高。

24. 发明授权

US06933192B1 Method for fabricating a trench having a buried dielectric collar 失效
标题翻译：一种用于制造具有埋入式电介质套环的沟槽的方法
公开(公告)号：US06933192B1
公开(公告)日：2005-08-23
申请号：US10709472
申请日：2004-05-07
申请人： Ramachandra Divakaruni , Ravikumar Ramachandran , Chun-Yung Sung
发明人： Ramachandra Divakaruni , Ravikumar Ramachandran , Chun-Yung Sung
IPC分类号： H01L21/334 , H01L21/8242 , H01L29/94
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A method of forming a buried dielectric collar around a trench and of forming a trench capacitor, the buried dielectric collar formed by: (a) forming the trench in a substrate; (b) forming a multilayer coating on sidewalls and a bottom of the trench; (c) removing a continuous band of the multilayer coating from the sidewalls a fixed distance from a top of the trench to expose a continuous band substrate in the sidewalls of the trench; (d) etching, in said exposed band of substrate, a lateral trench extending into said substrate in said sidewalls of said trench; and (e) filling the lateral trench with a dielectric material to form the buried dielectric collar. The trench capacitor is formed by filling the trench or its variants with polysilicon.
摘要翻译：一种在沟槽周围形成埋置的介电环圈并形成沟槽电容器的方法，所述埋入介质套管由以下部分形成：（a）在衬底中形成沟槽; （b）在沟槽的侧壁和底部上形成多层涂层; （c）从沟槽的顶部固定的距离从侧壁去除多层涂层的连续带，以暴露在沟槽的侧壁中的连续带状衬底; （d）在所述衬底的所述暴露带中蚀刻在所述沟槽的所述侧壁中延伸到所述衬底中的横向沟槽; 和（e）用电介质材料填充横向沟槽以形成埋入的电介质套环。通过用多晶硅填充沟槽或其变体形成沟槽电容器。

25. 发明授权

US06908806B2 Gate metal recess for oxidation protection and parasitic capacitance reduction 失效
标题翻译：栅极金属凹槽用于氧化保护和寄生电容降低
公开(公告)号：US06908806B2
公开(公告)日：2005-06-21
申请号：US10355726
申请日：2003-01-31
申请人： Haining Yang , Ramachandra Divakaruni , Oleg Gluschenkov , Rajeev Malik , Hongwen Yan , Ravikumar Ramachandran
发明人： Haining Yang , Ramachandra Divakaruni , Oleg Gluschenkov , Rajeev Malik , Hongwen Yan , Ravikumar Ramachandran
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28247 , H01L21/28061 , H01L21/76838
摘要： A method of fabricating a semiconductor device having a gate stack structure that includes gate stack sidewall, the gate stack structure having one or more metal layers comprising a gate metalis provided. The gate metal is recessed away from the gate stack sidewall using a chemical etch. The gate metal of the gate stack structure is selectively oxidized to form a metal oxide that at least partly fills the recess.
摘要翻译：一种制造半导体器件的方法，该半导体器件具有包括栅极叠层侧壁的栅极叠层结构，栅叠层结构具有一个或多个包含栅极金属的金属层。栅极金属通过化学蚀刻从栅极堆叠侧壁凹入。门堆叠结构的栅极金属被选择性地氧化以形成至少部分地填充凹部的金属氧化物。

26. 发明授权

US06849153B2 Removal of post-rie polymer on A1/CU metal line 有权
标题翻译：去除A1 / CU金属线上的后聚合物
公开(公告)号：US06849153B2
公开(公告)日：2005-02-01
申请号：US09204706
申请日：1998-12-03
申请人： Ravikumar Ramachandran , Wesley Natzle , Martin Gutsche , Hiroyuki Akatsu , Chien Yu
发明人： Ravikumar Ramachandran , Wesley Natzle , Martin Gutsche , Hiroyuki Akatsu , Chien Yu
IPC分类号： H01L21/302 , G03F7/42 , H01L21/02 , H01L21/027 , H01L21/306 , H01L21/3065 , H01L21/3205 , H01L21/3213 , C23F1/08
CPC分类号： H01L21/02071 , H01L21/02054 , H01L21/31138 , H01L21/32136 , Y10S134/902
摘要： A method for removal of post reactive ion etch sidewall polymer rails on a Al/Cu metal line of a semiconductor or microelectronic composite structure comprising: 1) supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber in which said composite structure is supported to form a water soluble material of sidewall polymer rails left behind on the Al/Cu metal line from the RIE process; removing the water soluble material with deionized water; and removing photo-resist from said composite structure by either a water-only plasma process or a chemical down stream etching method; or 2) forming a water-only plasma process to strip the photo-resist layer of a semiconductor or microelectronic composite structure previously subjected to a RIE process; supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber on which said structure is supported to form a water soluble material of saidwall polymer rails left behind on the Al/Cu metal line from the RIE process; and removing the water soluble material with deionized water.
摘要翻译：一种用于去除在半导体或微电子复合结构的Al / Cu金属线上的反应活性离子蚀刻侧壁聚合物轨道的方法，包括：1）将蚀刻气体和酸中和气体的混合物供应到真空室中，其中所述复合材料结构被支撑以形成从RIE工艺在Al / Cu金属线上留下的侧壁聚合物轨道的水溶性材料; 用去离子水去除水溶性物质; 以及通过水纯等离子体工艺或化学下游蚀刻方法从所述复合结构中除去光致抗蚀剂; 或2）形成仅水性等离子体工艺以剥离先前经受RIE工艺的半导体或微电子复合结构的光致抗蚀剂层;将蚀刻气体和酸中和气体的混合物供应到真空室中，在真空室中，被支撑以形成从RIE工艺在Al / Cu金属线上留下的所述壁聚合物轨道的水溶性材料; 并用去离子水去除水溶性物质。

27. 发明授权

US06723611B2 Vertical hard mask 失效
标题翻译：垂直硬面罩
公开(公告)号：US06723611B2
公开(公告)日：2004-04-20
申请号：US10241225
申请日：2002-09-10
申请人： Hiroyuki Akatsu , Oleg Gluschenkov , Porshia S. Parkinson , Ravikumar Ramachandran , Helmut Horst Tews , Kenneth T. Settlemyer, Jr.
发明人： Hiroyuki Akatsu , Oleg Gluschenkov , Porshia S. Parkinson , Ravikumar Ramachandran , Helmut Horst Tews , Kenneth T. Settlemyer, Jr.
IPC分类号： H01L2120
CPC分类号： H01L27/1087
摘要： In the course of forming a trench capacitor or similar structure, the sidewalls of an aperture in a substrate are lined with a film stack containing a diffusion barrier; an upper portion of the outer layer is stripped, so that the upper and lower portions have different materials exposed; the lower portion of the film stack is stripped while the upper portion is protected by a hardmask layer; a diffusion step is performed in the lower portion while the upper portion is protected; and a selected material such as hemispherical grained silicon is deposited selectively on the lower portion while the exposed surface of the upper portion is a material on which the selected material forms poorly, so that the diffusing material penetrates and the selected material is formed only on the lower portion.
摘要翻译：在形成沟槽电容器或类似结构的过程中，衬底中的孔的侧壁衬有包含扩散阻挡层的膜堆叠; 外层的上部被剥离，使得上部和下部具有不同的材料暴露; 薄膜堆叠的下部被剥离，同时上部被硬掩模层保护; 在上部被保护的同时在下部进行扩散步骤; 并且选择性地将选择的材料如半球形硅沉积在下部上，而上部的暴露表面是选择的材料形成不良的材料，使得扩散材料渗透，并且所选择的材料仅形成在下部。

28. 发明授权

US06569769B1 Slurry-less chemical-mechanical polishing 有权
标题翻译：无浆化学机械抛光
公开(公告)号：US06569769B1
公开(公告)日：2003-05-27
申请号：US09702311
申请日：2000-10-31
申请人： Laertis Economikos , Alexander Simpson , Ravikumar Ramachandran
发明人： Laertis Economikos , Alexander Simpson , Ravikumar Ramachandran
IPC分类号： H01L21302
CPC分类号： H01L21/31053
摘要： The invention provides slurry-less chemical-mechanical polishing processes which are effective in planarizing oxide materials, especially siliceous oxides, even where the starting oxide layer has significant topographical variation. The processes of the invention are preferably characterized by the use of a fixed abrasive polishing element and by use of an aqueous liquid medium containing a polyelectrolyte for at least a portion of the polishing process involving reduction in the amount of topographic variation (height differential) across the oxide material on the substrate. The method reduces or eliminates the transfer of topographic variations to levels below the desired planarization level. The processes enable elimination of special endpoint detection techniques. The processes are also especially suitable for polishing interlevel dielectrics.
摘要翻译：本发明提供无浆化学机械抛光方法，其有效平坦化氧化物材料，特别是硅氧化物，即使起始氧化物层具有显着的形貌变化。本发明的方法优选的特征在于使用固定的研磨抛光元件，并且通过使用含有聚电解质的含水液体介质，用于抛光过程的至少一部分，包括减少跨越的地形变化量（高差）衬底上的氧化物材料。该方法减少或消除了地形变化的转移到低于期望的平坦化水平的水平。这些过程能够消除特殊的端点检测技术。该工艺也特别适用于抛光层间电介质。

29. 发明授权

US06358855B1 Clean method for recessed conductive barriers 有权
标题翻译：凹陷导电屏障的清洁方法
公开(公告)号：US06358855B1
公开(公告)日：2002-03-19
申请号：US09595795
申请日：2000-06-16
申请人： Ravikumar Ramachandran , Nicolas Nagel , Christopher C. Parks
发明人： Ravikumar Ramachandran , Nicolas Nagel , Christopher C. Parks
IPC分类号： H01L21302
CPC分类号： H01L21/76849 , H01L21/02074 , H01L21/3212 , H01L21/32134 , H01L21/76861 , H01L21/7687 , H01L27/10855
摘要： A method for cleaning an oxidized diffusion barrier layer, in accordance with the present invention, includes providing a conductive diffusion barrier layer employed for preventing oxygen and metal diffusion therethrough and providing a wet chemical etchant including hydrofluoric acid. The diffusion barrier layer is etched with the wet chemical etchant to remove oxides from the diffusion barrier layer such that by employing the wet chemical etchant linear electrical behavior is achieved through the diffusion barrier layer.
摘要翻译：根据本发明的用于清洁氧化扩散阻挡层的方法包括提供用于防止氧和金属扩散的导电扩散阻挡层，并提供包括氢氟酸在内的湿化学蚀刻剂。用湿化学蚀刻剂蚀刻扩散阻挡层以从扩散阻挡层去除氧化物，使得通过使用湿化学蚀刻剂，通过扩散阻挡层实现线性电性能。

30. 发明授权

US06350692B1 Increased polish removal rate of dielectric layers using fixed abrasive pads 有权
标题翻译：使用固定磨料垫提高介电层的抛光去除率
公开(公告)号：US06350692B1
公开(公告)日：2002-02-26
申请号：US09737198
申请日：2000-12-14
申请人： Laertis Economikos , Ravikumar Ramachandran , Alexander Simpson
发明人： Laertis Economikos , Ravikumar Ramachandran , Alexander Simpson
IPC分类号： H01L21302
CPC分类号： H01L21/31053
摘要： A method for polishing a dielectric layer containing silicon provides a fluorine-based inorganic compound during a polishing process. The dielectric layer is polished in the presence of the fluorine based compound to accelerate a polishing rate of the dielectric layer.
摘要翻译：用于抛光含硅介电层的方法在抛光过程中提供氟基无机化合物。在氟基化合物的存在下对电介质层进行研磨，以加速电介质层的研磨速度。

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