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21. 发明申请

US20100005218A1 ENHANCED CASCADE INTERCONNECTED MEMORY SYSTEM 审中-公开
标题翻译：增强的CASCADE互连存储系统
公开(公告)号：US20100005218A1
公开(公告)日：2010-01-07
申请号：US12165816
申请日：2008-07-01
申请人： Kevin C. Gower , Paul W. Coteus , Warren E. Maule , Robert B. Tremaine
发明人： Kevin C. Gower , Paul W. Coteus , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F12/06
CPC分类号： G06F13/4234
摘要： A system, memory hub device, method and design structure for providing an enhanced cascade interconnected memory system are provided. The system includes a memory controller, a memory channel, a memory hub device coupled to the memory channel to communicate with the memory controller via one of a direct connection and a cascade interconnection through another memory hub device, and multiple memory devices in communication with the memory controller via one or more cascade interconnected memory hub devices. The memory channel includes unidirectional downstream link segments coupled to the memory controller and operable for transferring configurable data frames. The memory channel further includes unidirectional upstream link segments coupled to the memory controller and operable for transferring data frames.
摘要翻译：提供了一种用于提供增强级联互连存储器系统的系统，存储器集线器设备，方法和设计结构。该系统包括存储器控制器，存储器通道，耦合到存储器通道的存储器集线器设备，以经由另一个存储器集线器设备的直接连接和级联互连中的一个与存储器控制器进行通信，以及与存储控制器通信的多个存储器设备存储器控制器经由一个或多个级联互连的存储器集线器设备。存储器通道包括耦合到存储器控制器并且可操作用于传输可配置数据帧的单向下游链路段。存储器通道还包括耦合到存储器控制器并且可操作用于传送数据帧的单向上游链路段。

22. 发明申请

US20100005214A1 ENHANCING BUS EFFICIENCY IN A MEMORY SYSTEM 审中-公开
标题翻译：在存储系统中提高总线效率
公开(公告)号：US20100005214A1
公开(公告)日：2010-01-07
申请号：US12165814
申请日：2008-07-01
申请人： Michael R. Trombley , Kevin C. Gower , Warren E. Maule
发明人： Michael R. Trombley , Kevin C. Gower , Warren E. Maule
IPC分类号： G06F13/42 , G06F13/36
CPC分类号： G06F13/405 , G06F13/4243 , G06F13/4256 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for enhancing bus efficiency and utilization in a memory system. The communication interface device includes a first bus interface to communicate on a high-speed bus, a second bus interface to communicate on a lower-speed bus, and clock ratio logic configurable to support multiple clock ratios between the high-speed bus and the lower-speed bus. The clock ratio logic reduces a high-speed clock frequency received at the first bus interface and outputs a reduced ratio of the high-speed clock frequency on the lower-speed bus via the second bus interface supporting variable frame sizes.
摘要翻译：一种用于提高存储系统中总线效率和利用率的通信接口设备，系统，方法和设计结构。通信接口设备包括用于在高速总线上通信的第一总线接口，用于在低速总线上进行通信的第二总线接口以及可配置为支持高速总线与低速总线之间的多个时钟比的时钟比率逻辑高速公交车时钟比率逻辑降低了在第一总线接口处接收的高速时钟频率，并且经由支持可变帧大小的第二总线接口输出低速总线上的高速时钟频率的减小的比率。

23. 发明申请

US20100003837A1 276-PIN BUFFERED MEMORY MODULE WITH ENHANCED MEMORY SYSTEM INTERCONNECT AND FEATURES 有权
标题翻译：具有增强的存储器系统的276引脚缓冲存储器模块互连和特性
公开(公告)号：US20100003837A1
公开(公告)日：2010-01-07
申请号：US12166227
申请日：2008-07-01
申请人： Karl D. Loughner , Kevin C. Gower , Charles A. Kilmer , Warren E. Maule
发明人： Karl D. Loughner , Kevin C. Gower , Charles A. Kilmer , Warren E. Maule
IPC分类号： H01R12/00
CPC分类号： G11C5/04 , H01R12/721
摘要： A memory subsystem system including a rectangular printed circuit card having a first side and a second side, a length of between 149.5 and 153.5 millimeters, and first and second ends having a width smaller than the length. The memory system also includes a first plurality of pins on the first side extending along a first edge of the card that extends the length of the card, and a second plurality of pins on the second side extending on the first edge of the card. The memory system further includes a positioning key having it center positioned on the first edge of the card and located between 84.5 and 88.5 millimeters from the first end of the card and located between 62.5 and 66.5 millimeters from the second end of the card.
摘要翻译：一种存储器子系统，包括具有第一侧和第二侧的矩形印刷电路卡，长度在149.5和153.5毫米之间，第一和第二端具有小于该长度的宽度。存储器系统还包括在第一侧上沿着延长卡的长度的卡的第一边缘延伸的第一多个销，以及在卡的第一边缘上延伸的第二侧上的第二多个销。存储系统还包括定位键，其中心位于卡的第一边缘上，并位于距离卡的第一端84.5至88.5毫米之间，并位于距卡的第二端62.5至66.5毫米之间。

24. 发明申请

US20090216985A1 METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR DYNAMIC SELECTIVE MEMORY MIRRORING 有权
标题翻译：用于动态选择记忆镜的方法，系统和计算机程序产品
公开(公告)号：US20090216985A1
公开(公告)日：2009-08-27
申请号：US12035695
申请日：2008-02-22
申请人： James A. O'Connor , Kanwal Bahri , Daniel J. Henderson , Luis A. Lastras-Montano , Warren E. Maule , Michael Mueller , Naresh Nayar , Richard Nicholas , Eric E. Retter , William J. Starke , Michael R. Trombley , Kenneth L. Wright
发明人： James A. O'Connor , Kanwal Bahri , Daniel J. Henderson , Luis A. Lastras-Montano , Warren E. Maule , Michael Mueller , Naresh Nayar , Richard Nicholas , Eric E. Retter , William J. Starke , Michael R. Trombley , Kenneth L. Wright
IPC分类号： G06F12/02
CPC分类号： G06F11/1666 , G06F11/1076 , G06F11/20 , G06F12/0246 , G06F2211/1088
摘要： Methods, systems, and computer program products are provided for dynamic selective memory mirroring in solid state devices. An amount of memory is reserved. Sections of the memory to select for mirroring in the reserved memory are dynamically determined. The selected sections of the memory contain critical areas. The selected sections of the memory are mirrored in the reserved memory.
摘要翻译：为固态设备中的动态选择性存储器镜像提供了方法，系统和计算机程序产品。保留一定量的内存。用于在保留的存储器中选择镜像的存储器的部分是动态确定的。存储器的选定部分包含关键区域。存储器的选定部分被镜像在保留的存储器中。

25. 发明申请

US20090193203A1 System to Reduce Latency by Running a Memory Channel Frequency Fully Asynchronous from a Memory Device Frequency 失效
标题翻译：通过运行存储器通道频率从存储器件频率完全异步的系统来减少延迟
公开(公告)号：US20090193203A1
公开(公告)日：2009-07-30
申请号：US12019043
申请日：2008-01-24
申请人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
发明人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F13/4243
摘要： A memory system is provided that reduces latency by running a memory channel fully asynchronous from a memory device frequency. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency. The memory system also comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented. The first operating frequency is a maximum designed operating frequency of the memory channel and the first operating frequency is independent of the second operating frequency.
摘要翻译：提供了一种通过从存储器件频率运行完全异步的存储器通道来减少延迟的存储器系统。存储器系统包括集成在存储器模块中的存储器集线器设备。存储器集线器设备包括命令队列，其经由存储器通道以第一工作频率从外部存储器控制器接收存储器访问命令。存储器系统还包括集成在存储器集线器设备中的存储器集线器控制器。存储器集线器控制器以第二工作频率从命令队列读取存储器访问命令。通过以第一工作频率接收存储器访问命令并且以第二工作频率读取存储器访问命令，实现异步边界。第一个工作频率是存储器通道的最大设计工作频率，第一个工作频率与第二个工作频率无关。

26. 发明申请

US20090190429A1 System to Provide Memory System Power Reduction Without Reducing Overall Memory System Performance 失效
标题翻译：系统提供内存系统功耗而不降低整体内存系统性能
公开(公告)号：US20090190429A1
公开(公告)日：2009-07-30
申请号：US12018952
申请日：2008-01-24
申请人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
发明人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
IPC分类号： G11C8/18
CPC分类号： G11C5/04 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F13/4243 , G11C8/18 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/159
摘要： A memory system is provided that provides memory system power reduction without reducing overall memory system performance. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command from an memory controller via a memory channel at a first operating frequency. The memory system also comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented. Using the asynchronous boundary, the memory channel operates at a maximum designed operating bandwidth while the second operating frequency is independently decreased to reduce power being consumed by the set of memory devices.
摘要翻译：提供了一种提供存储器系统功率降低而不降低整体存储器系统性能的存储器系统。存储器系统包括集成在存储器模块中的存储器集线器设备。存储器集线器设备包括命令队列，其经由存储器通道以第一工作频率从存储器控制器接收存储器访问命令。存储器系统还包括集成在存储器集线器设备中的存储器集线器控制器。存储器集线器控制器以第二工作频率从命令队列读取存储器访问命令。通过以第一工作频率接收存储器访问命令并且以第二工作频率读取存储器访问命令，实现异步边界。使用异步边界，存储器通道以最大设计的工作带宽工作，而第二工作频率被独立地降低以减少由该组存储器件消耗的功率。

27. 发明授权

US07539800B2 System, method and storage medium for providing segment level sparing 有权
标题翻译：系统，方法和存储介质，用于提供段级备份
公开(公告)号：US07539800B2
公开(公告)日：2009-05-26
申请号：US10903188
申请日：2004-07-30
申请人： Timothy J. Dell , Frank D. Ferraiolo , Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
发明人： Timothy J. Dell , Frank D. Ferraiolo , Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
IPC分类号： G06F13/00 , G06F11/00
CPC分类号： G06F11/201 , G06F11/104
摘要： A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.
摘要翻译：一个内存子系统，包括段级备份。存储器子系统包括具有段级保护的级联互连系统。级联互连系统包括两个或多个存储器组件和存储器总线。存储器总线包括多个段，并且存储器组件经由存储器总线互连。

28. 发明授权

US07512762B2 System, method and storage medium for a memory subsystem with positional read data latency 失效
标题翻译：具有位置读数据延迟的存储器子系统的系统，方法和存储介质
公开(公告)号：US07512762B2
公开(公告)日：2009-03-31
申请号：US10977038
申请日：2004-10-29
申请人： Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
发明人： Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F13/1673 , G06F13/1689
摘要： A memory subsystem with positional read data latency that includes a cascaded interconnect system with one or more memory modules, a memory controller and one or more memory busses. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the memory busses.
摘要翻译：具有位置读数据延迟的存储器子系统，其包括具有一个或多个存储器模块的级联互连系统，存储器控制器和一个或多个存储器总线。存储器控制器包括用于提供位置读取数据等待时间的指令。存储器模块和存储器控制器通过分组化的多传输接口经由存储器总线互连。

29. 发明申请

US20090063922A1 System for Performing Error Correction Operations in a Memory Hub Device of a Memory Module 失效
标题翻译：用于在存储器模块的存储器集线器设备中执行纠错操作的系统
公开(公告)号：US20090063922A1
公开(公告)日：2009-03-05
申请号：US11848349
申请日：2007-08-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F11/00
CPC分类号： G06F11/1008
摘要： A memory system is provided for performing error correction operations in a memory module. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises a link interface integrated into the memory hub device that provides a communication pathway between an external memory controller and the set of memory devices. The memory hub device also comprises error correction logic integrated in the memory hub device and coupled to the link interface. The error correction logic performs error correction operations on data transferred between the link interface and the set of memory devices. The memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code.
摘要翻译：提供了一种用于在存储器模块中执行纠错操作的存储器系统。存储器系统包括集成在存储器模块中的存储器集线器设备和耦合到存储器集线器设备的一组存储器设备。存储器集线器设备包括集成到存储器集线器设备中的链路接口，其提供外部存储器控制器和该组存储器设备之间的通信路径。存储器集线器设备还包括集成在存储器集线器设备中并耦合到链路接口的纠错逻辑。误差校正逻辑对在链路接口和存储器件组之间传送的数据执行纠错操作。存储器集线器件通过外部存储器控制器和链路接口之间的存储器通道发送和接收数据，而没有任何纠错码。

30. 发明申请

US20080005496A1 Memory Systems for Automated Computing Machinery 有权
标题翻译：自动计算机存储系统
公开(公告)号：US20080005496A1
公开(公告)日：2008-01-03
申请号：US11383989
申请日：2006-05-18
申请人： Daniel M. Dreps , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Daniel M. Dreps , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F13/00
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.
摘要翻译：公开了包括存储器控制器和与存储器控制器连接到出站链路的出站链路的存储器系统。出站链路通常包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器件的多个导电路径; 以及在第一存储器层中的至少两个存储缓冲器件。第一存储器层中的每个存储器缓冲器件通常连接到出站链路以从存储器控制器接收存储器信号。

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