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21. 发明申请

US20120268566A1 THREE-DIMENSIONAL COLOR IMAGE SENSORS HAVING SPACED-APART MULTI-PIXEL COLOR REGIONS THEREIN 审中-公开
标题翻译：三维彩色图像传感器，其间隔多个像素颜色区域
公开(公告)号：US20120268566A1
公开(公告)日：2012-10-25
申请号：US13450761
申请日：2012-04-19
申请人： Won-Joo Kim , Yoon-Dong Park , Hyoung-Soo Ko
发明人： Won-Joo Kim , Yoon-Dong Park , Hyoung-Soo Ko
IPC分类号： H04N13/02
CPC分类号： H04N5/3745 , H04N5/3696 , H04N9/045 , H04N13/254
摘要： A three-dimensional color image sensor includes color pixels and depth pixels therein. A semiconductor substrate is provided with a depth region therein, which extends adjacent a surface of the semiconductor substrate. A two-dimensional array of spaced-apart color regions are provided within the depth region. Each of the color regions includes a plurality of different color pixels therein (e.g., red, blue and green pixels) and each of the color pixels within each of the spaced-apart color regions are spaced-apart from all other color pixels within other color regions.
摘要翻译：三维彩色图像传感器包括其中的彩色像素和深度像素。半导体衬底在其中设置有深度区域，其在半导体衬底的表面附近延伸。在深度区域内设置间隔开的彩色区域的二维阵列。每个颜色区域在其中包括多个不同的颜色像素（例如，红色，蓝色和绿色像素），并且每个间隔开的颜色区域内的每个彩色像素与其他颜色内的所有其他颜色像素间隔开地区。

22. 发明申请

US20110074989A1 IMAGE SENSORS 有权
标题翻译：图像传感器
公开(公告)号：US20110074989A1
公开(公告)日：2011-03-31
申请号：US12887258
申请日：2010-09-21
申请人： Eric R. Fossum , Soo-Jung Hwang , Young-Gu Jin , Yoon-Dong Park , Dae-Kil Cha
发明人： Eric R. Fossum , Soo-Jung Hwang , Young-Gu Jin , Yoon-Dong Park , Dae-Kil Cha
IPC分类号： H04N5/335 , H01L27/146
CPC分类号： H04N5/3696 , H01L27/14621 , H01L27/14645 , H04N5/2257 , H04N5/332
摘要： Provided is an image sensor having a depth sensor. The image sensor includes a substrate including a visible light region and a non-visible light region, a first well and a second well having a first conductivity type and in the non-visible light perception region, and a first gate and a second gate configured to receive voltages of opposite phases, respectively, and apply voltages to the first well and the second well, respectively.
摘要翻译：具有深度传感器的图像传感器。图像传感器包括：包括可见光区域和不可见光区域的基板，具有第一导电类型的第一阱和第二阱以及不可见光感知区域中的第一栅极和第二栅极配置分别接收相位相的电压，并分别向第一阱和第二阱施加电压。

23. 发明授权

US07652308B2 Semiconductor device having gate-all-around structure and method of fabricating the same 有权
标题翻译：具有栅极全绕结构的半导体器件及其制造方法
公开(公告)号：US07652308B2
公开(公告)日：2010-01-26
申请号：US11653863
申请日：2007-01-17
申请人： Yoon-Dong Park , Suk-Pil Kim
发明人： Yoon-Dong Park , Suk-Pil Kim
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/78639
摘要： Semiconductor devices having a gate-all-around (GAA) structure capable of higher operating performance may be provided. A semiconductor device may include a semiconductor substrate, at least one gate electrode, and at least one gate insulating layer. The semiconductor substrate may have a body, at least one supporting post protruding from the body, and at least one pair of fins separated from the body, wherein both ends of each fin of the at least one pair of fins are connected to and supported by the at least one supporting post. The at least one gate electrode may enclose a portion of at least one fin of the at least one pair of fins of the semiconductor substrate, and may be insulated from the semiconductor substrate. The at least one gate insulating layer may be interposed between the at least one gate electrode and the at least one pair of fins of the semiconductor substrate.
摘要翻译：可以提供具有能够具有更高操作性能的全能（GAA）结构的半导体器件。半导体器件可以包括半导体衬底，至少一个栅电极和至少一个栅极绝缘层。半导体衬底可以具有本体，从主体突出的至少一个支撑柱和与主体分离的至少一对翅片，其中至少一对翅片的每个翅片的两端连接并由其支撑所述至少一个支撑柱。至少一个栅电极可以包围半导体衬底的至少一对散热片中的至少一个鳍片的一部分，并且可以与半导体衬底绝缘。所述至少一个栅极绝缘层可以插入在所述至少一个栅电极和所述半导体衬底的所述至少一对鳍之间。

24. 发明申请

US20090315084A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：半导体器件和半导体衬底
公开(公告)号：US20090315084A1
公开(公告)日：2009-12-24
申请号：US12472951
申请日：2009-05-27
申请人： Dae-kil Cha , Won-Joo Kim , Tae-Hee Lee , Yoon-Dong Park
发明人： Dae-kil Cha , Won-Joo Kim , Tae-Hee Lee , Yoon-Dong Park
IPC分类号： H01L29/73 , H01L29/06 , H01L29/78 , H01L21/306
CPC分类号： H01L29/7841 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203
摘要： A semiconductor device includes a semiconductor substrate, a gate pattern disposed on the semiconductor substrate, a body region disposed on the gate pattern and a first impurity doping region and a second impurity doping region. The gate pattern is disposed below the body region and the first impurity doping region and the second impurity doping region.
摘要翻译：半导体器件包括半导体衬底，设置在半导体衬底上的栅极图案，设置在栅极图案上的主体区域和第一杂质掺杂区域以及第二杂质掺杂区域。栅极图案设置在主体区域和第一杂质掺杂区域和第二杂质掺杂区域的下方。

25. 发明申请

US20080293215A1 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
公开(公告)号：US20080293215A1
公开(公告)日：2008-11-27
申请号：US12219737
申请日：2008-07-28
申请人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
发明人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
IPC分类号： H01L21/76
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10873 , H01L27/10879 , H01L27/1159 , H01L27/2436 , H01L29/66795
摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.

26. 发明授权

US07439566B2 Semiconductor memory device having metal-insulator transition film resistor 有权
标题翻译：具有金属 - 绝缘体转移膜电阻器的半导体存储器件
公开(公告)号：US07439566B2
公开(公告)日：2008-10-21
申请号：US11485340
申请日：2006-07-13
申请人： Jae-Woong Hyun , In-Kyeong Yoo , Yoon-Dong Park , Choong-Rae Cho , Sung-Il Cho
发明人： Jae-Woong Hyun , In-Kyeong Yoo , Yoon-Dong Park , Choong-Rae Cho , Sung-Il Cho
IPC分类号： H01L29/06
CPC分类号： H01L27/108 , H01L27/101 , H01L27/2436 , H01L45/146
摘要： A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a first end of a metal-insulator transition film resistor, and at least one electrode of the capacitor may be connected to a second end of the metal-insulator transition film resistor. The metal-insulator transition film resistor may transition between an insulator and a conductor according to a voltage supplied to the first and second ends thereof.
摘要翻译：半导体存储器件可以具有较低的漏电流和/或更高的可靠性，例如较长的保留时间和/或更短的刷新时间。该装置可以包括开关装置和电容器。开关器件的源极可以连接到金属 - 绝缘体转变膜电阻器的第一端，并且电容器的至少一个电极可以连接到金属 - 绝缘体转变膜电阻器的第二端。金属 - 绝缘体转变膜电阻器可以根据提供给其第一和第二端的电压在绝缘体和导体之间转变。

27. 发明申请

US20070103963A1 Non-volatile memory devices and method thereof 有权
标题翻译：非易失性存储器件及其方法
公开(公告)号：US20070103963A1
公开(公告)日：2007-05-10
申请号：US11490129
申请日：2006-07-21
申请人： Won-Joo Kim , Sung-Jae Byun , Yoon-Dong Park , Eun-Hong Lee , Suk-Pil Kim , Jae-Woong Hyun
发明人： Won-Joo Kim , Sung-Jae Byun , Yoon-Dong Park , Eun-Hong Lee , Suk-Pil Kim , Jae-Woong Hyun
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C16/0416 , G11C2213/31 , G11C2213/32 , G11C2213/72 , H01L27/11521 , H01L27/11568
摘要： Non-volatile memory devices and a method thereof are provided. A non-volatile memory device according to an example embodiment of the present invention may include a first transistor including a source, a drain, and a control gate, a first storage node coupled to the first transistor, the first storage node configured to store information in a first manner, a first diode having a first end connected to the source of the transistor, the first diode configured to rectify a flow of current from the source of the transistor and a second storage node connected to a second end of the first diode, the second storage node configured to store information in a second manner. Another non-volatile memory device according to another example embodiment of the present invention may include a semiconductor substrate having a first conductivity type including an active region defined by a device isolating layer, a source region and a drain region formed by doping an impurity having a second conductivity type in the active region, a control gate electrode insulated from the active region, the control gate electrode extending across the active region disposed between the source region and the drain region, a first storage node layer interposed between the active region and the control gate electrode configured to store information in a first manner, a second storage node layer disposed on the source region configured to store information in a second manner and a diode interposed between the source region and the second storage node layer to rectify a flow of current to the source region. The example method may be directed to obtaining a higher storage capacity per cell area in either of the above-described example non-volatile memory devices.
摘要翻译：提供了非易失性存储器件及其方法。根据本发明的示例性实施例的非易失性存储器件可以包括：第一晶体管，包括源极，漏极和控制栅极;耦合到第一晶体管的第一存储节点，第一存储节点，被配置为存储信息以第一方式，第一二极管具有连接到晶体管的源极的第一端，第一二极管被配置为对来自晶体管的源极的电流进行整流，以及连接到第一二极管的第二端的第二存储节点所述第二存储节点被配置为以第二方式存储信息。根据本发明的另一示例性实施例的另一非易失性存储器件可以包括具有第一导电类型的半导体衬底，该第一导电类型包括由器件隔离层限定的有源区，源区和漏区，有源区中的第二导电类型，与有源区绝缘的控制栅电极，跨越设置在源区和漏区之间的有源区延伸的控制栅电极，插入在有源区和控制区之间的第一存储节点层栅电极，其被配置为以第一方式存储信息;第二存储节点层，被布置在源区域上，被配置为以第二方式存储信息;以及二极管，插入在源区域和第二存储节点层之间，以将电流流向源区域。示例性方法可以针对在上述任一示例非易失性存储器件中获得每个单元区域的更高的存储容量。

28. 发明申请

US20070018237A1 Non-volatile memory device having fin-type channel region and method of fabricating the same 审中-公开
标题翻译：具有鳍型沟道区的非易失性存储器件及其制造方法
公开(公告)号：US20070018237A1
公开(公告)日：2007-01-25
申请号：US11489445
申请日：2006-07-20
申请人： Won-Joo Kim , Suk-Pil Kim , Yoon-Dong Park , Eun-Hong Lee , Jae-Woong Hyun , Sung-Jae Byun , Jung-Hoon Lee
发明人： Won-Joo Kim , Suk-Pil Kim , Yoon-Dong Park , Eun-Hong Lee , Jae-Woong Hyun , Sung-Jae Byun , Jung-Hoon Lee
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/40114 , H01L29/40117 , H01L29/7851 , H01L29/792
摘要： A non-volatile memory device with improved integration and/or improved performance by reducing an area per bit and controlling a body bias, and a method of fabricating the same. The non-volatile memory device may use surface portions of the outer side surfaces and/or the upper surfaces of at least one pair of fins protruding from a body and extending, spaced from each other along one direction, as at least one pair of channel regions. At least one control gate electrode may be formed across the channel regions, and at least one pair of storage nodes may be interposed in at least one portion between the control gate electrode and the channel regions.
摘要翻译：具有通过减少每位面积和控制体偏置而具有改进的集成度和/或改善性能的非易失性存储器件及其制造方法。非挥发性存储装置可以使用从主体突出的至少一对翅片的外侧表面和/或上表面的表面部分，并且沿着一个方向彼此间隔开，作为至少一对通道地区。可以在沟道区域之间形成至少一个控制栅电极，并且可以在控制栅电极和沟道区域之间的至少一个部分中插入至少一对存储节点。

29. 发明申请

US20060145240A1 Memory devices and methods of operating the same 审中-公开
标题翻译：内存设备及操作方法
公开(公告)号：US20060145240A1
公开(公告)日：2006-07-06
申请号：US11325599
申请日：2006-01-05
申请人： Yoon-Dong Park , Won-Joo Kim , Sang-Hun Jeon
发明人： Yoon-Dong Park , Won-Joo Kim , Sang-Hun Jeon
IPC分类号： H01L29/788
CPC分类号： G11C13/0007 , G11C11/005 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C16/04 , G11C2213/31 , G11C2213/32 , H01L27/115 , H01L29/40114 , H01L29/40117 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： A memory device may include a first memory unit and a second memory unit. The first memory unit may include a first storage node storing data using a first method. The second memory unit may include a second storage node using a second method. The second method may be different than the first method, and the first memory unit and the second memory unit may share a source and a drain.
摘要翻译：存储器设备可以包括第一存储器单元和第二存储器单元。第一存储器单元可以包括使用第一方法存储数据的第一存储节点。第二存储器单元可以包括使用第二方法的第二存储节点。第二种方法可以不同于第一种方法，并且第一存储器单元和第二存储器单元可以共享源极和漏极。

30. 发明授权

US09225922B2 Image-sensing devices and methods of operating the same 有权
标题翻译：图像感测装置及其操作方法
公开(公告)号：US09225922B2
公开(公告)日：2015-12-29
申请号：US13550838
申请日：2012-07-17
申请人： Tae-Yon Lee , Yoon-Dong Park , Yong-Jei Lee , Seoung-Hyun Kim , Joo-Yeong Gong , Sung-Kwon Hong
发明人： Tae-Yon Lee , Yoon-Dong Park , Yong-Jei Lee , Seoung-Hyun Kim , Joo-Yeong Gong , Sung-Kwon Hong
IPC分类号： H04N5/357 , H04N5/378 , H04N5/369 , H04N5/3745
CPC分类号： H04N5/357 , H04N5/3696 , H04N5/3745 , H04N5/378
摘要： In a method of operating an image sensor, a noise voltage of a floating diffusion region is sampled after a reset voltage is applied to the floating diffusion region. A storage region, in which a photo-charge is stored, is electrically connected to the floating diffusion region after sampling the noise voltage, and a demodulation voltage of the floating diffusion region is sampled after the storage region and the floating diffusion region are electrically-connected. A voltage is determined based on the noise voltage and the demodulation voltage.
摘要翻译：在操作图像传感器的方法中，在对浮动扩散区域施加复位电压之后，对浮动扩散区域的噪声电压进行采样。在对噪声电压进行采样之后，存储光电荷的存储区域与浮动扩散区域电连接，并且在存储区域和浮动扩散区域电气化之后对浮动扩散区域的解调电压进行采样，连接的。基于噪声电压和解调电压确定电压。

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