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21. 发明授权

US08217450B1 Double-gate semiconductor device with gate contacts formed adjacent sidewalls of a fin 有权
标题翻译：双栅半导体器件，其栅极触点形成在翅片的相邻侧壁处
公开(公告)号：US08217450B1
公开(公告)日：2012-07-10
申请号：US10770011
申请日：2004-02-03
申请人： Bin Yu , Shibly S. Ahmed , Haihong Wang
发明人： Bin Yu , Shibly S. Ahmed , Haihong Wang
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/7855 , H01L29/7856
摘要： A double-gate semiconductor device includes a substrate, an insulating layer, a fin and two gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. A first gate is formed on the insulating layer and is adjacent a first sidewall of the fin. The second gate is formed on the insulating layer and is adjacent a second sidewall of the fin opposite the first sidewall. The first and second gates both include a conductive material and are electrically separated by the fin.
摘要翻译：双栅半导体器件包括衬底，绝缘层，鳍和两个栅极。绝缘层形成在基板上，并且鳍形成在绝缘层上。第一栅极形成在绝缘层上并与鳍片的第一侧壁相邻。第二栅极形成在绝缘层上并且与第一侧壁相对的翅片的第二侧壁相邻。第一和第二栅极都包括导电材料并且被散热片电隔离。

22. 发明授权

US07235436B1 Method for doping structures in FinFET devices 有权
标题翻译： FinFET器件掺杂结构的方法
公开(公告)号：US07235436B1
公开(公告)日：2007-06-26
申请号：US10614051
申请日：2003-07-08
申请人： Ming-Ren Lin , Zoran Krivokapic , Haihong Wang , Bin Yu
发明人： Ming-Ren Lin , Zoran Krivokapic , Haihong Wang , Bin Yu
IPC分类号： H01L21/84
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A method for doping fin structures in FinFET devices includes forming a first glass layer on the fin structure of a first area and a second area. The method further includes removing the first glass layer from the second area, forming a second glass layer on the fin structure of the first area and the second area, and annealing the first area and the second area to dope the fin structures.
摘要翻译：在FinFET器件中掺杂鳍结构的方法包括在第一区域和第二区域的鳍结构上形成第一玻璃层。该方法还包括从第二区域去除第一玻璃层，在第一区域和第二区域的翅片结构上形成第二玻璃层，并退火第一区域和第二区域以掺杂翅片结构。

23. 发明授权

US07112847B1 Smooth fin topology in a FinFET device 有权
标题翻译： FinFET器件中的平滑鳍拓扑
公开(公告)号：US07112847B1
公开(公告)日：2006-09-26
申请号：US10653227
申请日：2003-09-03
申请人： Bin Yu , Haihong Wang
发明人： Bin Yu , Haihong Wang
IPC分类号： H01L27/01
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/42384 , H01L29/4908 , H01L29/66795 , Y10S257/90
摘要： A semiconductor device includes a semiconductor fin formed on an insulator and sidewall spacers formed adjacent the sides of the fin. A gate material layer is formed over the fin and the sidewall spacers and etched to form a gate. The presence of the sidewall spacers causes a topology of the gate material layer to smoothly transition over the fin and the first and second sidewall spacers.
摘要翻译：半导体器件包括形成在绝缘体上的半导体鳍片和邻近翅片侧面形成的侧壁间隔物。栅极材料层形成在鳍片和侧壁间隔物上并被蚀刻以形成栅极。侧壁间隔物的存在导致栅极材料层的拓扑结构平滑地过渡翅片和第一和第二侧壁间隔物。

24. 发明授权

US07041601B1 Method of manufacturing metal gate MOSFET with strained channel 有权
标题翻译：制造具有应变通道的金属栅极MOSFET的方法
公开(公告)号：US07041601B1
公开(公告)日：2006-05-09
申请号：US10653103
申请日：2003-09-03
申请人： Bin Yu , Haihong Wang
发明人： Bin Yu , Haihong Wang
IPC分类号： H01L21/311
CPC分类号： H01L29/7842 , H01L29/4908 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A method of manufacturing a MOSFET type semiconductor device includes forming a fin structure and a dummy gate structure over the fin structure. Sidewall spacers may be formed adjacent the dummy gate structure. The dummy gate structure may be later removed and replaced with a metal layer that is formed at a high temperature (e.g., 600°–700° C.). The cooling of the metal layer induces strain to the fin structure that affects the mobility of the double-gate MOSFET.
摘要翻译：制造MOSFET型半导体器件的方法包括在鳍结构上形成翅片结构和虚拟栅极结构。侧壁间隔件可以与伪栅极结构相邻地形成。可以稍后去除虚拟栅极结构并用在高温（例如600℃-700℃）下形成的金属层代替。金属层的冷却会引起对鳍结构的应变，从而影响双栅极MOSFET的迁移率。

25. 发明授权

US06958512B1 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US06958512B1
公开(公告)日：2005-10-25
申请号：US10770010
申请日：2004-02-03
申请人： Yider Wu , Shibly S. Ahmed , Haihong Wang , Bin Yu
发明人： Yider Wu , Shibly S. Ahmed , Haihong Wang , Bin Yu
IPC分类号： H01L21/336 , H01L29/423 , H01L29/786 , H01L29/788
CPC分类号： H01L29/42324 , H01L29/66795 , H01L29/785 , H01L29/7881
摘要： A non-volatile memory device includes a substrate, an insulating layer, a fin, a conductive structure and a control gate. The insulating layer may be formed on the substrate and the fin may be formed on the insulating layer. The conductive structure may be formed near a side of the fin and the control gate may be formed over the fin. The conductive structure may act as a floating gate electrode for the non-volatile memory device.
摘要翻译：非易失性存储器件包括衬底，绝缘层，鳍，导电结构和控制栅。绝缘层可以形成在基板上，并且鳍可以形成在绝缘层上。导电结构可以形成在鳍的一侧附近，并且控制栅可以形成在翅片上。导电结构可以用作非易失性存储器件的浮栅电极。

26. 发明授权

US06933558B2 Flash memory device 有权
标题翻译：闪存设备
公开(公告)号：US06933558B2
公开(公告)日：2005-08-23
申请号：US10726508
申请日：2003-12-04
申请人： Wiley Eugene Hill , Haihong Wang , Yider Wu , Bin Yu
发明人： Wiley Eugene Hill , Haihong Wang , Yider Wu , Bin Yu
IPC分类号： G11C16/04 , H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/792
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/785
摘要： A memory device includes a conductive structure, a number of dielectric layers and a control gate. The dielectric layers are formed around the conductive structure and the control gate is formed over the dielectric layers. A portion of the conductive structure functions as a drain region for the memory device and at least one of the dielectric layers functions as a charge storage structure for the memory device. The dielectric layers may include oxide-nitride-oxide layers.
摘要翻译：存储器件包括导电结构，多个电介质层和控制栅极。电介质层形成在导电结构周围，并且控制栅极形成在电介质层上。导电结构的一部分用作存储器件的漏极区，并且至少一个介电层用作存储器件的电荷存储结构。电介质层可以包括氧化物 - 氮化物 - 氧化物层。

27. 发明授权

US06897527B2 Strained channel FinFET 有权
标题翻译：应变通道FinFET
公开(公告)号：US06897527B2
公开(公告)日：2005-05-24
申请号：US10833112
申请日：2004-04-28
申请人： Srikanteswara Dakshina-Murthy , Judy Xilin An , Zoran Krivokapic , Haihong Wang , Bin Yu
发明人： Srikanteswara Dakshina-Murthy , Judy Xilin An , Zoran Krivokapic , Haihong Wang , Bin Yu
IPC分类号： H01L21/336 , H01L29/10 , H01L29/49 , H01L29/786 , H01L27/01
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/4908 , H01L29/66795 , H01L29/78654 , H01L29/78687
摘要： A semiconductor device includes a fin and a layer formed on at least a portion of the fin. The fin includes a first crystalline material. The layer includes a second crystalline material, where the first crystalline material has a larger lattice constant than the second crystalline material to induce tensile strain within the layer.
摘要翻译：半导体器件包括翅片和形成在鳍片的至少一部分上的层。翅片包括第一结晶材料。该层包括第二结晶材料，其中第一结晶材料具有比第二结晶材料更大的晶格常数以在层内引起拉伸应变。

28. 发明授权

US06893930B1 Fabrication of field effect transistor with shallow junctions using low temperature activation of antimony 有权
标题翻译：使用低温活化锑制造具有浅结的场效应晶体管
公开(公告)号：US06893930B1
公开(公告)日：2005-05-17
申请号：US10161452
申请日：2002-05-31
申请人： Bin Yu , Haihong Wang
发明人： Bin Yu , Haihong Wang
IPC分类号： H01L21/265 , H01L21/336
CPC分类号： H01L29/66598 , H01L21/26513 , H01L29/665 , H01L29/6653
摘要： For fabricating a field effect transistor on an active device area of a semiconductor substrate, a gate dielectric and a gate electrode are formed on the active device area of the semiconductor substrate. Antimony (Sb) dopant is implanted into exposed regions of the active device area of the semiconductor substrate to form at least one of drain and source extension junctions and/or drain and source contact junctions. A low temperature thermal anneal process at a temperature less than about 950° Celsius is performed for activating the antimony (Sb) dopant within the drain and source extension junctions and/or drain and source contact junctions. In one embodiment of the present invention, the drain and source contact junctions are formed and thermally annealed before the formation of the drain and source extension junctions in a disposable spacer process for further minimizing heating of the drain and source extension junctions. In another embodiment of the present invention, the drain and source extension junctions and/or the drain and source contact junctions are formed to be amorphous before the thermal anneal process. In that case, a SPE (solid phase epitaxy) activation process in performed for activating the antimony (Sb) dopant within the amorphous drain and source extension junctions and/or the amorphous drain and source contact junctions at a temperature less than about 650° Celsius.
摘要翻译：为了在半导体衬底的有源器件区域上制造场效应晶体管，在半导体衬底的有源器件区域上形成栅极电介质和栅电极。将锑（Sb）掺杂剂注入到半导体衬底的有源器件区域的暴露区域中，以形成漏极和源极延伸结和/或漏极和源极接触结中的至少一个。在低于约950℃的温度下进行低温热退火工艺，以激活漏极和源极延伸结和/或漏极和源极接触接点内的锑（Sb）掺杂剂。在本发明的一个实施例中，在一次性间隔器工艺中形成漏极和源极延伸接头之前，形成漏极和源极接触接头并进行热退火，以进一步最小化漏极和源极延伸接点的加热。在本发明的另一实施例中，在热退火工艺之前，将漏极和源极延伸接头和/或漏极和源极接触接点形成为非晶体。在这种情况下，在低于约650℃的温度下，在非晶漏极和源极延伸结和/或非晶漏极和源极接触点内激活用于激活锑（Sb）掺杂剂的SPE（固相外延）激活过程。

29. 发明授权

US06812119B1 Narrow fins by oxidation in double-gate finfet 有权
标题翻译：狭窄的翅片通过氧化在双门finfet
公开(公告)号：US06812119B1
公开(公告)日：2004-11-02
申请号：US10614052
申请日：2003-07-08
申请人： Shibly S. Ahmed , Ming-Ren Lin , Haihong Wang , Bin Yu
发明人： Shibly S. Ahmed , Ming-Ren Lin , Haihong Wang , Bin Yu
IPC分类号： H01L213205
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/7842
摘要： A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first layer of semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.
摘要翻译：一种形成双栅极鳍效应晶体管（FinFET）的鳍片的方法包括在第一半导体材料层上形成第二半导电材料层，并在第二半导体材料层中形成双重盖子。该方法还包括在每个双盖的侧面上形成间隔物，并在双重帽下面的第一半导体材料层中形成双翅片。该方法还包括使双翅片变薄以产生窄的双翅片。

30. 发明授权

US06787406B1 Systems and methods for forming dense n-channel and p-channel fins using shadow implanting 有权
标题翻译：使用阴影植入形成致密的n通道和p通道翅片的系统和方法
公开(公告)号：US06787406B1
公开(公告)日：2004-09-07
申请号：US10638334
申请日：2003-08-12
申请人： Wiley Eugene Hill , Shibly S. Ahmed , Haihong Wang , Bin Yu
发明人： Wiley Eugene Hill , Shibly S. Ahmed , Haihong Wang , Bin Yu
IPC分类号： H01L2184
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/66803 , Y10S438/944
摘要： A method facilitates the doping of fins of a semiconductor device that includes a substrate. The method includes forming fin structures on the substrate, where each of the fin structures includes a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first one of the fins with n-type impurities and performing a second tilt angle implant process to dope a second one of the fins with p-type impurities.
摘要翻译：一种方法有助于掺杂包括衬底的半导体器件的散热片。该方法包括在基板上形成翅片结构，其中每个翅片结构都包括形成在翅片上的盖。该方法还包括执行第一倾斜角度注入工艺以用n型杂质掺杂第一个翅片，并执行第二倾斜角度注入工艺，以使p型杂质掺杂第二个翅片。

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