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21. 发明申请

US20120187980A1 TRANSMITTER CIRCUIT 失效
标题翻译：发射机电路
公开(公告)号：US20120187980A1
公开(公告)日：2012-07-26
申请号：US13358324
申请日：2012-01-25
申请人： Hiroaki KURAHASHI , Tomofumi Hokari , Takashi Muto , Goichi Ono , Hiroki Yamashita
发明人： Hiroaki KURAHASHI , Tomofumi Hokari , Takashi Muto , Goichi Ono , Hiroki Yamashita
IPC分类号： H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018514
摘要： A transmitter circuit in which a driver circuit includes MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input controlled by a voltage value of transmitted data signals, controlled by a voltage value of a bias voltage, and driver circuits include MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input that is controlled by a voltage value of signals obtained by the transmitted data signals, connected to a load portion, and controlled by a voltage value of a bias voltage.
摘要翻译：一种发射机电路，其中驱动电路包括用于偏压施加的MOS晶体管，其中驱动电流流动，共源共栅连接到MOS晶体管，用于由传输数据信号的电压值控制的差分信号输入，由电压值偏置电压和驱动电路包括用于偏置电压施加的MOS晶体管，其中驱动电流流动，共源共栅连接到用于差分信号输入的MOS晶体管，该MOS晶体管由通过发送的数据信号获得的信号的电压值控制，连接到负载部分，并由偏置电压的电压值控制。

22. 发明申请

US20110316632A1 OPTICAL COMMUNICATION DEVICE 有权
标题翻译：光通信设备
公开(公告)号：US20110316632A1
公开(公告)日：2011-12-29
申请号：US13201212
申请日：2009-03-05
申请人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
发明人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
IPC分类号： H03F3/16 , H03F1/22 , H03G3/20
CPC分类号： H03F3/087 , H03F1/223 , H03F1/34 , H03F3/082 , H03F3/3022 , H03F3/505 , H03F2200/453 , H04B10/6933
摘要： An optical communication device which can be operated at high speed is provided. For example, the optical communication device includes: a pre-amplifier circuit PREAMP1 amplifying a current signal Iin from a photodiode PD, and converting an amplified signal into a voltage signal; and an operating-point controller circuit VTCTL1 controlling an operation of the PREAMP1. The PREAMP1 includes a negative feedback path formed by a feedback resistance Rf1, and includes: a level-shift circuit LS1 level-shifting in accordance with an operating-point control signal Vcon; and an amplifier circuit AMP1 connected to a subsequent stage of the LS1 and performing an amplifying operation with a high gain. The VTCTL1 includes a replica circuit configured by the same circuit and circuit parameter as those of the AMP1 and electrically connected between the input and the output, and generates the Vcon so that an output DC level of this replica circuit is matched with an input DC level of the AMP1.
摘要翻译：提供可以高速运转的光通信装置。例如，光通信装置包括：前置放大器电路PREAMP1，放大来自光电二极管PD的电流信号Iin，将放大后的信号变换为电压信号; 以及控制PREAMP1的操作的操作点控制器电路VTCTL1。 PREAMP1包括由反馈电阻Rf1形成的负反馈路径，并且包括：根据工作点控制信号Vcon的电平移位电路LS1电平移位; 以及连接到LS1的后级并且以高增益进行放大操作的放大器电路AMP1。 VTCTL1包括由与AMP1相同的电路和电路参数配置的电路复用电路，并且电连接在输入和输出端之间，并产生Vcon，使得该复制电路的输出直流电平与输入直流电平相匹配的AMP1。

23. 发明授权

US07764090B2 Semiconductor device having transmitter/receiver circuit between circuit blocks 失效
标题翻译：在电路块之间具有发射机/接收机电路的半导体器件
公开(公告)号：US07764090B2
公开(公告)日：2010-07-27
申请号：US12105586
申请日：2008-04-18
申请人： Hiroki Yamashita , Ryo Nemoto
发明人： Hiroki Yamashita , Ryo Nemoto
IPC分类号： H03K3/00
CPC分类号： H03K19/018557
摘要： A receiver circuit includes first and second constant current sources respectively connected to a pair of first and second receiving terminals to receive complementary current signals, a first NMOS transistor connected at a source thereof to the first receiving terminal and the first constant current source and connected at a drain thereof to a first power supply via a first output terminal and first load means, and a second NMOS transistor connected at a source thereof to the second receiving terminal and the second constant current source and connected at a drain thereof to the first power supply via a second output terminal and second load means.
摘要翻译：接收器电路包括分别连接到一对第一和第二接收端子以接收互补电流信号的第一和第二恒定电流源，连接到其源极的第一NMOS晶体管与第一接收端子和第一恒定电流源连接，其漏极经由第一输出端子和第一负载装置到第一电源，以及第二NMOS晶体管，其源极连接到第二接收端子和第二恒流源，并在其漏极处连接到第一电源经由第二输出端子和第二负载装置。

24. 发明申请

US20090296851A1 Pre-emphasis circuit 有权
标题翻译：预加重电路
公开(公告)号：US20090296851A1
公开(公告)日：2009-12-03
申请号：US12453981
申请日：2009-05-28
申请人： Goichi Ono , Hiroki Yamashita
发明人： Goichi Ono , Hiroki Yamashita
IPC分类号： H04L27/00
CPC分类号： H04L25/0272
摘要： A pre-emphasis circuit which can improve a communication quality of a data transmission at low cost is provided. A current switch circuit, a current adder circuit, and transition detection circuits are provided in a transmitter of a data transmission system. The transition detection circuits detect transitions of transmission data signals which are a differential pair. The current switch circuit receives the transmission data signals, carries driving currents in accordance with the transmission data signals, and outputs output data signals which are a differential pair. The current adder circuit receives detection signals from the transition detection circuits, and adds driving currents in accordance with the detection signals to load resistors. By this means, output data signals in which the transitions are emphasized are inputted to a transmission line.
摘要翻译：提供了可以以低成本提高数据传输的通信质量的预加重电路。电流开关电路，电流加法器电路和转移检测电路设置在数据传输系统的发射机中。转移检测电路检测作为差分对的发送数据信号的转变。电流开关电路接收发送数据信号，根据发送数据信号传送驱动电流，并输出作为差分对的输出数据信号。电流加法器电路接收来自转换检测电路的检测信号，并根据检测信号将驱动电流加到负载电阻上。通过这种方式，将转换强调的输出数据信号输入到传输线。

25. 发明授权

US07535261B2 Logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：US07535261B2
公开(公告)日：2009-05-19
申请号：US11492894
申请日：2006-07-26
申请人： Fumio Yuuki , Hiroki Yamashita
发明人： Fumio Yuuki , Hiroki Yamashita
IPC分类号： H03K19/20 , H03K19/094 , H03K17/16 , H03K19/003 , H03K19/0175
CPC分类号： H03K3/356043 , H03K3/012
摘要： A first current source generating a current I0+I when a control signal is in ‘H’ level and a current I0 when it is in ‘L’ level, a current mirror circuit transferring a current generated in the first current source and composed of first and second MOS transistors, and a second current source connected to the second transistor and generating I0+I are provided. Further, a node branched from a connection node between the second transistor and the second current source is formed, and a logic unit including a flip-flop circuit formed of a differential amplifier is driven through the node. The logic unit is in an active state when the control signal is in ‘H’ level and it is in an inactive state when the signal is in ‘L’ level. When the logic unit is in an active state, it processes a data input signal to generate data output signal.
摘要翻译：当控制信号为“H”电平时产生电流I0 + I的第一电流源，当处于“L”电平时产生电流I0的电流镜像电路，传送在第一电流源中产生并由第一电流源和第二MOS晶体管，以及连接到第二晶体管并产生I0 + I的第二电流源。此外，形成从第二晶体管和第二电流源之间的连接节点分支的节点，并且包括由差分放大器形成的触发器电路的逻辑单元被驱动通过该节点。当控制信号为“H”电平时，逻辑单元处于活动状态，当信号处于“L”电平时，它处于非活动状态。当逻辑单元处于活动状态时，它处理数据输入信号以产生数据输出信号。

26. 发明授权

US07474720B2 Clock and data recovery method and digital circuit for the same 失效
标题翻译：时钟和数据恢复方法与数字电路相同
公开(公告)号：US07474720B2
公开(公告)日：2009-01-06
申请号：US10722484
申请日：2003-11-28
申请人： Fumio Yuuki , Hiroki Yamashita , Masahito Sonehara
发明人： Fumio Yuuki , Hiroki Yamashita , Masahito Sonehara
IPC分类号： H04L7/00 , H04J3/06
CPC分类号： H04L7/0331 , H03L7/0814 , H03L7/091 , H03L2207/50 , H04L7/0337
摘要： A clock data recovery circuit has a good jitter tolerance characteristic and a broad data recovery range in the event of a wander, that is, a good wander-tracking characteristic of a recovered clock signal. The clock data recovery circuit executes control to compare the position of the edge of data with the position of the edge of a data recovery clock signal (a recovered clock signal) and keeps the clock edge away from the data edge if a gap between the edges becomes smaller than a reference value. A cycle of a reference clock signal is divided into N portions to generate N clock signals (pl ) with phases different from each other in composition circuits. By executing control to turn on 2 of the N selector control signals supplied to each 2 adjacent pins of the N−1 selectors at the same time, the N−1 selectors are capable of generating a middle phase between first and second phases and, hence, generating one of N×2 phases from N input phases as the phase of the data recovery clock signal.
摘要翻译：时钟数据恢复电路在漂移的情况下具有良好的抖动容限特性和广泛的数据恢复范围，即，恢复的时钟信号的漂移跟踪特性良好。时钟数据恢复电路执行控制以将数据边缘的位置与数据恢复时钟信号（恢复的时钟信号）的边沿的位置进行比较，并且如果边缘之间的间隙保持时钟边缘远离数据边缘变得小于参考值。参考时钟信号的周期被分成N个部分，以在合成电路中产生具有彼此不同的相位的N个时钟信号（pl）。通过执行控制以同时接通提供给N-1个选择器的每个2个相邻引脚的N个选择器控制信号中的2个，N-1选择器能够在第一和第二相之间产生中间相位，因此从N个输入相位产生Nx2相位之一作为数据恢复时钟信号的相位。

27. 发明授权

US07417818B2 Magnetic recording device 失效
标题翻译：磁记录装置
公开(公告)号：US07417818B2
公开(公告)日：2008-08-26
申请号：US11342828
申请日：2006-01-31
申请人： Fumio Yuuki , Hiroki Yamashita , Masayoshi Yagyu , Tatsuya Kawashimo
发明人： Fumio Yuuki , Hiroki Yamashita , Masayoshi Yagyu , Tatsuya Kawashimo
IPC分类号： G11B5/02
CPC分类号： G11B5/486 , G11B5/484
摘要： A magnetic recording device capable of reducing the size of a writing circuit and the power consumption by readily adjusting the overshoot of the write current pulses is provided. Two or more transmission lines having different characteristic impedances are provided between an output driver having an impedance Zs and a magnetic head, the transmission lines are formed so that the characteristic impedances Z1, Zn−1, and Zn (n≧2) thereof on the output driver side are higher than those on the magnetic recording head side (Z1>Zn−1>Zn), and the impedance Zs of the output driver is equal to or higher than the characteristic impedance Z1 of the transmission line.
摘要翻译：提供了能够通过容易地调整写入电流脉冲的过冲来减小写入电路的尺寸和功耗的磁记录装置。具有不同特性阻抗的两条或更多条传输线被提供在具有阻抗Z S s的输出驱动器和磁头之间，传输线形成为使得特性阻抗Z 1 = 2）高于磁记录头侧（Z _{1 。}

28. 发明授权

US07183615B2 Nonvolatile semiconductor memory and manufacturing method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法相同
公开(公告)号：US07183615B2
公开(公告)日：2007-02-27
申请号：US10868773
申请日：2004-06-17
申请人： Hiroki Yamashita , Yoshio Ozawa , Atsuhiro Sato
发明人： Hiroki Yamashita , Yoshio Ozawa , Atsuhiro Sato
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0483 , H01L27/115 , H01L29/42324 , Y10T428/24256
摘要： A semiconductor memory has a memory cell matrix encompassing (a) device isolation films running along the column-direction, arranged alternately between the memory cell transistors aligned along the row-direction, (b) first conductive layers arranged along the row and column-directions, top surfaces of the first conductive layers lie at a lower level than top surfaces of the device isolation films, (c) an inter-electrode dielectric arranged both on the device isolation films and the first conductive layers so that the inter-electrode dielectric can be shared by the memory cell transistors belonging to different cell columns' relative dielectric constant of the inter-electrode dielectric is higher than relative dielectric constant of the device isolation films, and (d) a second conductive layer running along the row-direction, arranged on the inter-electrode dielectric. Here, upper corners of the device isolation films are chamfered.
摘要翻译：半导体存储器具有存储单元阵列，其包括（a）沿着列方向延伸的器件隔离膜，交替地布置在沿着行方向排列的存储单元晶体管之间，（b）沿行和列方向排列的第一导电层第一导电层的顶表面位于比器件隔离膜的顶表面更低的水平面上，（c）布置在器件隔离膜和第一导电层上的电极间电介质，使得电极间电介质可以由属于不同单元列的存储单元晶体管所共用，电极间电介质的相对介电常数高于器件隔离膜的相对介电常数，（d）沿着行方向延伸的第二导电层，在电极间电介质上。这里，器件隔离膜的上角被倒角。

29. 发明授权

US07046468B2 Semiconductor integrated circuit and magnetic storage device using the same 失效
标题翻译：半导体集成电路和使用其的磁存储器件
公开(公告)号：US07046468B2
公开(公告)日：2006-05-16
申请号：US11030067
申请日：2005-01-07
申请人： Hiroki Yamashita , Masayoshi Yagyu , Fumio Yuuki , Tatsuya Kawashimo
发明人： Hiroki Yamashita , Masayoshi Yagyu , Fumio Yuuki , Tatsuya Kawashimo
IPC分类号： G11B5/02
CPC分类号： G11B5/02 , B82Y10/00 , B82Y25/00 , G11B5/022 , G11B2005/0013 , G11B2005/3996 , H03K17/6872 , H03K2217/0036
摘要： The present invention provides a semiconductor integrated circuit capable of reducing a circuit area and a magnetic storage device using the same. The circuit in the present invention is provided with a single-stage output transistor for supplying write current to a magnetic head, a current source for outputting reference current of the write current, a diode-connected NMOS transistor for converting the current to gate voltage and having a certain device size ratio to the output transistor, a regulator circuit for transmitting gate voltage of the NMOS transistor and reducing output impedance, and a CMOS circuit for setting power supply voltage to an output of the regulator circuit and controlling the gate voltage of the output transistor. Then, this circuit is applied as a write circuit in a magnetic storage device.
摘要翻译：本发明提供能够减少电路面积的半导体集成电路和使用该半导体集成电路的磁存储装置。本发明的电路设置有用于向磁头提供写入电流的单级输出晶体管，用于输出写入电流的参考电流的电流源，用于将电流转换为栅极电压的二极管连接的NMOS晶体管，以及与输出晶体管具有一定的器件尺寸比，用于传输NMOS晶体管的栅极电压并降低输出阻抗的调节器电路，以及用于将电源电压设置到调节器电路的输出并控制调节器电路的栅极电压的CMOS电路输出晶体管。然后，该电路作为写入电路应用于磁存储装置。

30. 发明申请

US20050068066A1 Logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：US20050068066A1
公开(公告)日：2005-03-31
申请号：US10886035
申请日：2004-07-08
申请人： Hiroki Yamashita , Akio Koyama , Tatsuhiro Aida , Atsushi Itoh , Masahito Sonehara
发明人： Hiroki Yamashita , Akio Koyama , Tatsuhiro Aida , Atsushi Itoh , Masahito Sonehara
IPC分类号： H03K19/086 , H03F1/30 , H03F3/45 , H03K5/22 , H03K19/003 , H03K19/0944
CPC分类号： H03K19/00369 , H03F1/301 , H03K19/09448
摘要： The power supply-voltage dependency of a current source current is reduced and the power supply voltage is lowered. The invention includes an emitter-coupled logic circuit 118 and a reference-voltage generating circuit 119 for generating a reference voltage VCSC for controlling a drain current (=current source current ICS) of a constant current-supplying n-type MOS transistor 110. The emitter-coupled logic circuit 118 comprises a current switch made up of a pair of emitter-coupled bipolar transistors 106 and 107, a constant current-supplying n-type MOS transistor 110 that is connected in series with the current switch, and resistor means 108 and 109 connected in series with the bipolar transistors 106 and 107 individually for obtaining an output voltage. The reference-voltage generating circuit 119 comprises an n-type MOS transistor 111, a bipolar transistor 112 which determines the drain voltage of the n-type MOS transistor 111, and a control circuit 120 for controlling the drain current of the n-type MOS transistor 111.
摘要翻译：电流源电流的电源电压依赖性降低，电源电压降低。本发明包括发射极耦合逻辑电路118和参考电压产生电路119，用于产生用于控制恒流电源n型MOS晶体管110的漏极电流（=电流源电流ICS）的参考电压VCSC。发射极耦合逻辑电路118包括由一对发射极耦合双极晶体管106和107构成的电流开关，与电流开关串联连接的恒流供应n型MOS晶体管110和电阻器装置108 和109分别与双极晶体管106和107串联连接以获得输出电压。参考电压产生电路119包括n型MOS晶体管111，确定n型MOS晶体管111的漏极电压的双极晶体管112和用于控制n型MOS晶体管111的漏极电流的控制电路120 晶体管111。

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