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1. 发明申请

US20050207228A1 Semiconductor integrated circuit and magnetic storage device using the same 失效
标题翻译：半导体集成电路和使用其的磁存储器件
公开(公告)号：US20050207228A1
公开(公告)日：2005-09-22
申请号：US11030067
申请日：2005-01-07
申请人： Hiroki Yamashita , Masayoshi Yagyu , Fumio Yuuki , Tatsuya Kawashimo
发明人： Hiroki Yamashita , Masayoshi Yagyu , Fumio Yuuki , Tatsuya Kawashimo
IPC分类号： G11B5/09 , G11B5/00 , G11B5/012 , G11B5/02 , G11B5/39 , G11C16/06 , H03K17/00 , H03K17/687
CPC分类号： G11B5/02 , B82Y10/00 , B82Y25/00 , G11B5/022 , G11B2005/0013 , G11B2005/3996 , H03K17/6872 , H03K2217/0036
摘要： The present invention provides a semiconductor integrated circuit capable of reducing a circuit area and a magnetic storage device using the same. The circuit in the present invention is provided with a single-stage output transistor for supplying write current to a magnetic head, a current source for outputting reference current of the write current, a diode-connected NMOS transistor for converting the current to gate voltage and having a certain device size ratio to the output transistor, a regulator circuit for transmitting gate voltage of the NMOS transistor and reducing output impedance, and a CMOS circuit for setting power supply voltage to an output of the regulator circuit and controlling the gate voltage of the output transistor. Then, this circuit is applied as a write circuit in a magnetic storage device.
摘要翻译：本发明提供能够减少电路面积的半导体集成电路和使用该半导体集成电路的磁存储装置。本发明的电路设置有用于向磁头提供写入电流的单级输出晶体管，用于输出写入电流的参考电流的电流源，用于将电流转换为栅极电压的二极管连接的NMOS晶体管，以及与输出晶体管具有一定的器件尺寸比，用于传输NMOS晶体管的栅极电压并降低输出阻抗的调节器电路，以及用于将电源电压设置到调节器电路的输出并控制调节器电路的栅极电压的CMOS电路输出晶体管。然后，该电路作为写入电路应用于磁存储装置。

2. 发明授权

US07417818B2 Magnetic recording device 失效
标题翻译：磁记录装置
公开(公告)号：US07417818B2
公开(公告)日：2008-08-26
申请号：US11342828
申请日：2006-01-31
申请人： Fumio Yuuki , Hiroki Yamashita , Masayoshi Yagyu , Tatsuya Kawashimo
发明人： Fumio Yuuki , Hiroki Yamashita , Masayoshi Yagyu , Tatsuya Kawashimo
IPC分类号： G11B5/02
CPC分类号： G11B5/486 , G11B5/484
摘要： A magnetic recording device capable of reducing the size of a writing circuit and the power consumption by readily adjusting the overshoot of the write current pulses is provided. Two or more transmission lines having different characteristic impedances are provided between an output driver having an impedance Zs and a magnetic head, the transmission lines are formed so that the characteristic impedances Z1, Zn−1, and Zn (n≧2) thereof on the output driver side are higher than those on the magnetic recording head side (Z1>Zn−1>Zn), and the impedance Zs of the output driver is equal to or higher than the characteristic impedance Z1 of the transmission line.
摘要翻译：提供了能够通过容易地调整写入电流脉冲的过冲来减小写入电路的尺寸和功耗的磁记录装置。具有不同特性阻抗的两条或更多条传输线被提供在具有阻抗Z S s的输出驱动器和磁头之间，传输线形成为使得特性阻抗Z 1 = 2）高于磁记录头侧（Z _{1 。}

3. 发明授权

US07046468B2 Semiconductor integrated circuit and magnetic storage device using the same 失效
标题翻译：半导体集成电路和使用其的磁存储器件
公开(公告)号：US07046468B2
公开(公告)日：2006-05-16
申请号：US11030067
申请日：2005-01-07
申请人： Hiroki Yamashita , Masayoshi Yagyu , Fumio Yuuki , Tatsuya Kawashimo
发明人： Hiroki Yamashita , Masayoshi Yagyu , Fumio Yuuki , Tatsuya Kawashimo
IPC分类号： G11B5/02
CPC分类号： G11B5/02 , B82Y10/00 , B82Y25/00 , G11B5/022 , G11B2005/0013 , G11B2005/3996 , H03K17/6872 , H03K2217/0036
摘要： The present invention provides a semiconductor integrated circuit capable of reducing a circuit area and a magnetic storage device using the same. The circuit in the present invention is provided with a single-stage output transistor for supplying write current to a magnetic head, a current source for outputting reference current of the write current, a diode-connected NMOS transistor for converting the current to gate voltage and having a certain device size ratio to the output transistor, a regulator circuit for transmitting gate voltage of the NMOS transistor and reducing output impedance, and a CMOS circuit for setting power supply voltage to an output of the regulator circuit and controlling the gate voltage of the output transistor. Then, this circuit is applied as a write circuit in a magnetic storage device.
摘要翻译：本发明提供能够减少电路面积的半导体集成电路和使用该半导体集成电路的磁存储装置。本发明的电路设置有用于向磁头提供写入电流的单级输出晶体管，用于输出写入电流的参考电流的电流源，用于将电流转换为栅极电压的二极管连接的NMOS晶体管，以及与输出晶体管具有一定的器件尺寸比，用于传输NMOS晶体管的栅极电压并降低输出阻抗的调节器电路，以及用于将电源电压设置到调节器电路的输出并控制调节器电路的栅极电压的CMOS电路输出晶体管。然后，该电路作为写入电路应用于磁存储装置。

4. 发明授权

US07373114B2 Signal transmission circuit, signal output circuit and termination method of signal transmission circuit 有权
标题翻译：信号传输电路，信号输出电路和信号传输电路的终端方法
公开(公告)号：US07373114B2
公开(公告)日：2008-05-13
申请号：US11030063
申请日：2005-01-07
申请人： Masayoshi Yagyu , Hiroki Yamashita , Fumio Yuuki , Tatsuya Kawashimo
发明人： Masayoshi Yagyu , Hiroki Yamashita , Fumio Yuuki , Tatsuya Kawashimo
IPC分类号： H04B1/44
CPC分类号： H04B3/02 , H04L25/0282
摘要： This invention provides a signal transmission circuit, a signal output circuit, and a termination method of a signal transmission circuit capable of preventing the re-reflection of the signal at a transmitting node of a transmission path even when an impedance of a signal output circuit does not match a characteristic impedance of a transmission path. On a signal transmission circuit composed of a transmission path, a signal output circuit connected to a transmitting node of the transmission path, and a signal receiver circuit connected to a receiving node of the signal transmission path, in order to prevent the re-reflection of an output signal of a signal output unit at the transmitting node via the receiving node, a correction current generator unit is provided for outputting correction current with a predetermined current amount and at a predetermined timing set in a current amount/timing control section, to the transmitting node.
摘要翻译：本发明提供信号传输电路，信号输出电路和信号传输电路的终止方法，该信号传输电路即使在信号输出电路的阻抗发生时也能防止在传输路径的发射节点处的信号的再反射不符合传输路径的特性阻抗。在由传输路径组成的信号传输电路，连接到传输路径的发送节点的信号输出电路以及连接到信号传输路径的接收节点的信号接收器电路中，以防止重新反射经由接收节点在发送节点处的信号输出单元的输出信号，提供校正电流发生器单元，用于以预定电流量和在当前量/定时控制部分中设置的预定定时输出校正电流，发送节点。

5. 发明申请

US20060203372A1 Magnetic recording device 失效
标题翻译：磁记录装置
公开(公告)号：US20060203372A1
公开(公告)日：2006-09-14
申请号：US11342828
申请日：2006-01-31
申请人： Fumio Yuuki , Hiroki Yamashita , Masayoshi Yagyu , Tatsuya Kawashimo
发明人： Fumio Yuuki , Hiroki Yamashita , Masayoshi Yagyu , Tatsuya Kawashimo
IPC分类号： G11B5/02
CPC分类号： G11B5/486 , G11B5/484
摘要： A magnetic recording device capable of reducing the size of a writing circuit and the power consumption by readily adjusting the overshoot of the write current pulses is provided. Two or more transmission lines having different characteristic impedances are provided between an output driver having an impedance Zs and a magnetic head, the transmission lines are formed so that the characteristic impedances Z1, Zn−1, and Zn (n≧2) thereof on the output driver side are higher than those on the magnetic recording head side (Z1>Zn−1>Zn), and the impedance Zs of the output driver is equal to or higher than the characteristic impedance Z1 of the transmission line.
摘要翻译：提供了能够通过容易地调整写入电流脉冲的过冲来减小写入电路的尺寸和功耗的磁记录装置。具有不同特性阻抗的两条或更多条传输线被提供在具有阻抗Z S s的输出驱动器和磁头之间，传输线形成为使得特性阻抗Z 1 = 2）高于磁记录头侧（Z _{1 。}

6. 发明申请

US20050208902A1 Signal transmission circuit, signal output circuit and termination method of signal transmission circuit 有权
标题翻译：信号传输电路，信号输出电路和信号传输电路的终端方法
公开(公告)号：US20050208902A1
公开(公告)日：2005-09-22
申请号：US11030063
申请日：2005-01-07
申请人： Masayoshi Yagyu , Hiroki Yamashita , Fumio Yuuki , Tatsuya Kawashimo
发明人： Masayoshi Yagyu , Hiroki Yamashita , Fumio Yuuki , Tatsuya Kawashimo
IPC分类号： H03K19/0175 , G05F1/40 , G05F1/44 , G05F1/618 , H04B1/38 , H04B1/44 , H04B3/02 , H04L25/02
CPC分类号： H04B3/02 , H04L25/0282
摘要： This invention provides a signal transmission circuit, a signal output circuit, and a termination method of a signal transmission circuit capable of preventing the re-reflection of the signal at a transmitting node of a transmission path even when an impedance of a signal output circuit does not match a characteristic impedance of a transmission path. On a signal transmission circuit composed of a transmission path, a signal output circuit connected to a transmitting node of the transmission path, and a signal receiver circuit connected to a receiving node of the signal transmission path, in order to prevent the re-reflection of an output signal of a signal output unit at the transmitting node via the receiving node, a correction current generator unit is provided for outputting correction current with a predetermined current amount and at a predetermined timing set in a current amount/timing control section, to the transmitting node.
摘要翻译：本发明提供信号传输电路，信号输出电路和信号传输电路的终止方法，该信号传输电路即使在信号输出电路的阻抗发生时也能防止在传输路径的发射节点处的信号的再反射不符合传输路径的特性阻抗。在由传输路径组成的信号传输电路，连接到传输路径的发送节点的信号输出电路以及连接到信号传输路径的接收节点的信号接收器电路中，以防止重新反射经由接收节点在发送节点处的信号输出单元的输出信号，提供校正电流发生器单元，用于以预定电流量和在当前量/定时控制部分中设置的预定定时输出校正电流，发送节点。

7. 发明授权

US07319575B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07319575B2
公开(公告)日：2008-01-15
申请号：US11288323
申请日：2005-11-29
申请人： Tatsuya Kawashimo , Hiroki Yamashita , Masayoshi Yagyu
发明人： Tatsuya Kawashimo , Hiroki Yamashita , Masayoshi Yagyu
IPC分类号： H02H9/00 , H03K17/16
CPC分类号： H03F1/52 , H01L27/0266
摘要： This invention provides a semiconductor device in which an ESD protection circuit and a termination circuit can be realized with a small die area. A PMOS transistor having an ESD protection function is placed between a signal node on a line from an signal terminal to an input buffer and a supply voltage node. Furthermore, a voltage generator circuit is placed to supply a reference voltage to the gate of the PMOS transistor. By the reference voltage controlled by the voltage generator circuit, a source drain resistance of the PMOS transistor is set. Thereby, the PMOS transistor can be made to function as a terminating resistor whose resistance can be set adaptively to a characteristic impedance of a transmission line, for example, connected to the signal terminal in addition to the ESD protection function.
摘要翻译：本发明提供一种半导体器件，其中可以以小的裸片面积实现ESD保护电路和终端电路。具有ESD保护功能的PMOS晶体管被放置在从信号端到输入缓冲器的线路上的信号节点和电源电压节点之间。此外，放置电压发生器电路以向PMOS晶体管的栅极提供参考电压。通过由电压发生器电路控制的参考电压，设置PMOS晶体管的源极漏极电阻。由此，除了ESD保护功能之外，还可以使PMOS晶体管起到终端电阻的作用，该电阻的电阻可以适应于传输线的特性阻抗，例如连接到信号端。

8. 发明申请

US20060158802A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060158802A1
公开(公告)日：2006-07-20
申请号：US11288323
申请日：2005-11-29
申请人： Tatsuya Kawashimo , Hiroki Yamashita , Masayoshi Yagyu
发明人： Tatsuya Kawashimo , Hiroki Yamashita , Masayoshi Yagyu
IPC分类号： H02H9/00
CPC分类号： H03F1/52 , H01L27/0266
摘要： This invention provides a semiconductor device in which an ESD protection circuit and a termination circuit can be realized with a small die area. A PMOS transistor having an ESD protection function is placed between a signal node on a line from an signal terminal to an input buffer and a supply voltage node. Furthermore, a voltage generator circuit is placed to supply a reference voltage to the gate of the PMOS transistor. By the reference voltage controlled by the voltage generator circuit, a source-drain resistance of the PMOS transistor is set. Thereby, the PMOS transistor can be made to function as a terminating resistor whose resistance can be set adaptively to a characteristic impedance of a transmission line, for example, connected to the signal terminal in addition to the ESD protection function.
摘要翻译：本发明提供一种半导体器件，其中可以以小的裸片面积实现ESD保护电路和终端电路。具有ESD保护功能的PMOS晶体管被放置在从信号端到输入缓冲器的线路上的信号节点和电源电压节点之间。此外，放置电压发生器电路以向PMOS晶体管的栅极提供参考电压。通过由电压发生器电路控制的参考电压，设置PMOS晶体管的源极 - 漏极电阻。由此，除了ESD保护功能之外，还可以使PMOS晶体管起到终端电阻的作用，该电阻的电阻可以适应于传输线的特性阻抗，例如连接到信号端。

9. 发明授权

US5881078A Logic circuit having error detection function and processor including the logic circuit 失效
标题翻译：具有误差检测功能的逻辑电路和包括逻辑电路的处理器
公开(公告)号：US5881078A
公开(公告)日：1999-03-09
申请号：US989414
申请日：1997-12-12
申请人： Makoto Hanawa , Yoshio Miki , Tatsuya Kawashimo
发明人： Makoto Hanawa , Yoshio Miki , Tatsuya Kawashimo
IPC分类号： G06F11/00 , G06F11/08 , H03K19/00
CPC分类号： G06F11/085
摘要： Soft errors generated at an active time are reduced by adding a small-scale circuit to a high performance LSI, such as a processor without reducing the performance of the circuit. The processor has individual logic circuits each having a plurality of stages of logic gates for outputting true signals and complement signals for the individual logic gates. A latch circuit latches the true and complement signals of the logic circuits separately and a compare circuit detects for an error by comparing the true and complement output signals of the logic circuits to determine if they are at the same logical signal level or not, just upstream of the latch in which the individual true and complement output signals of the final logic circuit stages are individually latched. When the compare circuit detects an error because the true and complement output signals are at the same logical signal level, a recovery process is executed.
摘要翻译：通过向诸如处理器的高性能LSI添加小规模电路而不降低电路的性能来减少在活动时间产生的软错误。处理器具有各自具有用于输出各个逻辑门的真实信号和补码信号的多级逻辑门的单独逻辑电路。锁存电路分别锁存逻辑电路的真实和补码信号，比较电路通过比较逻辑电路的真实和补码输出信号来确定它们是否处于相同的逻辑信号电平，正好在上游其中最终逻辑电路级的各个真实和补码输出信号被单独锁存。当比较电路检测到误差是因为真实和补码输出信号处于相同的逻辑信号电平时，执行恢复处理。

10. 发明授权

US07127717B2 Hierarchical server system 有权
标题翻译：分级服务器系统
公开(公告)号：US07127717B2
公开(公告)日：2006-10-24
申请号：US10216846
申请日：2002-08-13
申请人： Tatsuya Kawashimo , Yoshio Miki , Hiroaki Fujii , Akihiro Takamura
发明人： Tatsuya Kawashimo , Yoshio Miki , Hiroaki Fujii , Akihiro Takamura
IPC分类号： G06F9/46 , G06F11/00 , G06F15/173
CPC分类号： H04L67/1008 , H04L29/06 , H04L67/1002 , H04L67/1029 , H04L69/329 , H04L2029/06054
摘要： A hierarchical server system efficiently balances the processing load thereon and for shortening the processing time therein is provided, such as a web server system. A system controller, a load balancing device, and a shared memory are provided in a multi-layer server system made of a plurality of servers. When processing implemented with a first layer server is temporarily stopped in order to acquire information needed for processing from a second layer server, process information needed to resume the processing is recorded in the shared memory. When the necessary information is sent back to the first layer server, the system controller inquires about work statuses of all first layer servers to select another first layer server to resume the processing based upon the inquiry results. The then selected first layer server then resumes the processing using the information that was sent back and the process information in the shared memory.
摘要翻译：分层服务器系统有效平衡其上的处理负担，并且缩短了其中的处理时间，诸如web服务器系统。在由多个服务器构成的多层服务器系统中提供系统控制器，负载平衡装置和共享存储器。当为了从第二层服务器获取处理所需的信息时，当暂时停止用第一层服务器实施的处理时，恢复处理所需的处理信息被记录在共享存储器中。当必要的信息被发送回第一层服务器时，系统控制器询问所有第一层服务器的工作状态，以选择另一个第一层服务器，以根据查询结果恢复处理。然后，所选择的第一层服务器使用发回的信息和共享存储器中的处理信息来恢复处理。

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