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    • 21. 发明授权
    • Method of manufacturing semiconductor device
    • 制造半导体器件的方法
    • US07115475B2
    • 2006-10-03
    • US11002638
    • 2004-12-03
    • Masakazu YamaguchiWataru SaitoIchiro OmuraMasaru Izumisawa
    • Masakazu YamaguchiWataru SaitoIchiro OmuraMasaru Izumisawa
    • H01I21/336
    • H01L29/7811H01L29/0634H01L29/0653H01L29/0696H01L29/402H01L29/41741H01L29/66712H01L29/7802
    • A method of manufacturing a semiconductor device in which a trench groove is formed in a first conductivity type semiconductor layer, and a second conductivity type semiconductor layer is epitaxially grown so as to bury the trench groove. The second conductivity type semiconductor layer is then removed until a surface of the first conductivity type semiconductor layer is exposed. The first conductivity type semiconductor layer is epitaxially grown on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer such that the thickness of the first conductivity type semiconductor layer increases by a length which is substantially the same as a depth of the trench groove. The first conductivity type semiconductor layer is selectively removed such that the second conductivity type semiconductor layer is exposed, and the epitaxially growing of the second conductivity type semiconductor layer is repeated through selectively removing the first conductivity type semiconductor layer.
    • 一种制造半导体器件的方法,其中在第一导电类型半导体层中形成沟槽槽,并且外延生长第二导电类型半导体层以便埋入沟槽。 然后去除第二导电类型半导体层直到露出第一导电类型半导体层的表面。 在第一导电类型半导体层和第二导电类型半导体层上外延生长第一导电类型半导体层,使得第一导电类型半导体层的厚度增加与沟槽的深度基本相同的长度 。 选择性地去除第一导电型半导体层,使得露出第二导电类型半导体层,并且通过选择性地去除第一导电类型半导体层来重复第二导电类型半导体层的外延生长。
    • 29. 发明授权
    • Power transistor
    • 功率晶体管
    • US06545341B2
    • 2003-04-08
    • US09817227
    • 2001-03-27
    • Masakazu Yamaguchi
    • Masakazu Yamaguchi
    • H01L27082
    • H01L29/73
    • The present invention relates to a constitution of a bipolar type power transistor, which comprises: a base layer of a first conductivity type; a collector layer of the first conductivity type formed on one surface of the base layer of the first conductivity type; a first base layer of a second conductivity type formed selectively on the other surface of the base layer of the first conductivity type; and a second base layer of the second conductivity type selectively formed on the other surface of the first conductivity type base layer. The second conductivity type base layer is formed in a divided manner, and each of the second conductivity type base layers are separated by the first conductivity type base layer.
    • 本发明涉及双极型功率晶体管的结构,其包括:第一导电类型的基极层; 形成在第一导电类型的基底层的一个表面上的第一导电类型的集电极层; 第一导电类型的第一基底层选择性地形成在第一导电类型的基底层的另一个表面上; 以及选择性地形成在第一导电型基底层的另一个表面上的第二导电类型的第二基底层。 第二导电型基层以分割的方式形成,并且每个第二导电型基底层被第一导电型基底层分开。
    • 30. 发明授权
    • Semiconductor device
    • 半导体电源mosfet器件带有载流子注入
    • US6114727A
    • 2000-09-05
    • US3829
    • 1998-01-07
    • Tsuneo OguraMasakazu Yamaguchi
    • Tsuneo OguraMasakazu Yamaguchi
    • H01L29/78H01L21/331H01L29/06H01L29/739H01L29/80H01L29/94
    • H01L29/7397H01L29/0696H01L29/66333H01L29/66348H01L29/7395
    • A semiconductor device comprises a high-resistance n type base layer, an n type drain layer formed on one surface of the n type base layer, p type base layers selectively formed at the other surface of the n type base layer, n type source layers selectively formed at surfaces of the p type base layers, p type injection layers selectively formed at the other surface of the n type base layer in regions different from regions where the n type source layers and p type base layers are formed, a trench selectively formed to extend from a surface of each n type source layer through the p type base layer into the n type base layer, a first gate electrode buried in the trench with an insulating film interposed, a drain electrode formed on the n type drain layer, a source electrode formed on the n type source layer, and a second gate electrode formed on the p type injection layer.
    • 半导体器件包括高电阻n型基极层,形成在n型基极层的一个表面上的n型漏极层,在n型基极层的另一个表面上选择性地形成的p型基极层,n型源极层 选择性地形成在p型基底层的表面上,在与n型源极层和p型基极层不同的区域中在n型基极层的另一个表面上选择性地形成p型注入层,选择性地形成沟槽 从每个n型源极层的表面穿过p型基极层延伸到n型基极层中,埋置在具有绝缘膜的沟槽中的第一栅电极,形成在n型漏极层上的漏电极, 形成在n型源极层上的源电极和形成在p型注入层上的第二栅电极。