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21. 发明申请

US20070194229A1 Method and apparatus for inspecting pattern defects and mirror electron projection Type or multi-beam scanning type electron beam apparatus 有权
标题翻译：用于检查图案缺陷和镜电子投影的方法和装置型或多光束扫描型电子束装置
公开(公告)号：US20070194229A1
公开(公告)日：2007-08-23
申请号：US11601723
申请日：2006-11-20
申请人： Hirohito Okuda , Takashi Hiroi , Masaki Hasegawa , Shigeya Tanaka
发明人： Hirohito Okuda , Takashi Hiroi , Masaki Hasegawa , Shigeya Tanaka
IPC分类号： G21K7/00
CPC分类号： H01J37/026 , H01J37/292 , H01J2237/0048 , H01J2237/2817
摘要： The present invention provides a mirror electron projection (MPJ) type (SEPJ type included) scanning electron beam apparatus that is capable of performing condition setup, and a method and apparatus for inspecting pattern defects with the scanning electron beam apparatus. A mirror electron projection type defect inspection apparatus, which comprises a charging device for emitting a charging electron beam, electron beam irradiation means for shedding a mirror electron projection electron beam onto an inspection region near which an electrical potential distribution is formed, detection means for detecting secondary electrons or reflected electrons generated from a surface and proximity of the specimen, and defect detection means for detecting a defect by processing a mirror image signal that is detected by the detection means, includes irradiation condition optimization means for optimizing charging electron beam irradiation conditions.
摘要翻译：本发明提供一种能够进行条件建立的镜电子投射（MPJ）型（包括SEPJ型）扫描电子束装置，以及用扫描电子束装置检查图案缺陷的方法和装置。镜电子投影型缺陷检查装置，其包括用于发射充电电子束的充电装置，用于将镜电子投影电子束切除到形成有电位分布的检查区域的电子束照射装置，用于检测从检体的表面和邻近产生的二次电子或反射电子，以及用于通过处理由检测装置检测出的镜像信号来检测缺陷的缺陷检测装置，包括用于优化充电电子束照射条件的照射条件优化装置。

22. 发明授权

US5894582A Method of controlling parallel processing at an instruction level and processor for realizing the method 失效
标题翻译：在指令级别控制并行处理的方法和用于实现该方法的处理器
公开(公告)号：US5894582A
公开(公告)日：1999-04-13
申请号：US596628
申请日：1996-02-05
申请人： Shoji Yoshida , Takashi Hotta , Shigeya Tanaka
发明人： Shoji Yoshida , Takashi Hotta , Shigeya Tanaka
IPC分类号： G06F9/38 , G06F9/28
CPC分类号： G06F9/3853
摘要： Apparatus for realizing instruction level parallel processing includes an instruction buffer for storing instructions fetched from a memory until the instructions are sent from the instruction buffer, an instruction register unit for storing and issuing the sent instructions to a plurality of execution units in the order of instruction, and a judgement part for judging whether it is possible to execute a set of unissued instructions to be next issued, in parallel, as stored in the instruction buffer and/or the instruction register unit and for controlling parallel processing of the set of instructions, based on the result of a judgement on the possibility of parallel processing.
摘要翻译：用于实现指令级并行处理的装置包括：指令缓冲器，用于存储从指令缓冲器发送指令之前从存储器取出的指令;指令寄存器单元，用于以指令顺序存储并发布发送指令给多个执行单元; 以及用于判断是否可以并行地执行存储在指令缓冲器和/或指令寄存器单元中并用于控制该组指令的并行处理的一组未发布指令的判断部分，基于对并行处理可能性的判断结果。

23. 发明授权

US5713012A Microprocessor 失效
标题翻译：微处理器
公开(公告)号：US5713012A
公开(公告)日：1998-01-27
申请号：US717143
申请日：1996-09-20
申请人： Shigeya Tanaka , Takashi Hotta , Shoji Yoshida , Kenji Jin , Koji Saito
发明人： Shigeya Tanaka , Takashi Hotta , Shoji Yoshida , Kenji Jin , Koji Saito
IPC分类号： G06F9/38 , G06F9/40
CPC分类号： G06F9/3836 , G06F9/3861 , G06F9/3885
摘要： A microprocessor has N processing units, a detector for detecting a branch instruction (k-th instruction) which comes first in the instruction sequence of N instructions, function logic for effecting control such that the first to the k-th instructions are executed with the (N-k+1)-th through the N-th processing units. However, when parallel processing is possible, the function logic operates such that the first through the N-th instructions are executed in sequential order by the first through the N-th processing units. On the other hand, wherein a branch instruction (k-th instruction) is included in the N sequential instructions, the function logic operates such that the first through the k-th instructions are parallelly executed by the (N-p+1)-th through the N-th processing units.
摘要翻译：微处理器具有N个处理单元，用于检测在N个指令的指令序列中首先出现的分支指令（第k指令）的检测器，用于进行控制的功能逻辑，使得第一到第k指令被执行（N-k + 1）到第N个处理单元。然而，当并行处理是可能的时候，功能逻辑操作使得第一到第N指令由第一到第N个处理单元按顺序执行。另一方面，其中在N个顺序指令中包括分支指令（第k指令），功能逻辑运算，使得第一至第k指令由（N-p + 1） - 通过第N个处理单元。

24. 发明授权

US5153452A Bipolar-MOS IC with internal voltage generator and LSI device with internal voltage generator 失效
标题翻译：具有内部电压发生器和具有内部电压发生器的LSI器件的双极MOS IC
公开(公告)号：US5153452A
公开(公告)日：1992-10-06
申请号：US401849
申请日：1989-08-30
申请人： Masahiro Iwamura , Shigeya Tanaka , Tatsumi Yamauchi , Ikuro Masuda , Tetsuo Nakano
发明人： Masahiro Iwamura , Shigeya Tanaka , Tatsumi Yamauchi , Ikuro Masuda , Tetsuo Nakano
IPC分类号： H01L27/04 , G05F1/46 , G11C5/14 , G11C11/401 , G11C11/407 , G11C11/56 , H01L21/822 , H01L27/06
CPC分类号： G11C11/565 , G05F1/465 , G11C5/147 , G11C16/30
摘要： There are provided a bipolar-MOS IC device smaller than half-micron scale, and a combination of such IC device and external circuits. The IC device has an internal voltage generating circuit for generating an internal power source by using an external power source, the voltage of the internal power source being lower than that of the external power source. The internal voltage generating circuit includes an NPN transistor formed in an N-type region or N-type island within a P-type semiconductor substrate of the IC device, and a PMOS transistor formed in the N-type island. The collector of the NPN transistor and the source of the PMOS transistor are used as external power source terminals. The drain of the PMOS transistor is connected to the base of the NPN transistor. The gate is used as a control signal terminal. The emitter of the NPN transistor is used as an internal power source output terminal. A current path from the external power source input terminal and the internal power source output terminal is accordingly formed within the N-type island isolated from the P-type substrate.
摘要翻译：提供了小于半微米级的双极MOS集成电路，以及这些IC器件和外部电路的组合。 IC器件具有内部电压产生电路，用于通过使用外部电源产生内部电源，内部电源的电压低于外部电源的电压。内部电压产生电路包括形成在IC器件的P型半导体衬底内的N型区域或N型岛中的NPN晶体管和形成在N型岛中的PMOS晶体管。 NPN晶体管的集电极和PMOS晶体管的源极用作外部电源端子。 PMOS晶体管的漏极连接到NPN晶体管的基极。门用作控制信号端子。 NPN晶体管的发射极用作内部电源输出端子。因此，在与P型基板隔离的N型岛中形成从外部电源输入端子和内部电源输出端子的电流路径。

25. 发明授权

US09164042B2 Device for detecting foreign matter and method for detecting foreign matter 有权
标题翻译：异物检测装置及异物检测方法
公开(公告)号：US09164042B2
公开(公告)日：2015-10-20
申请号：US13984286
申请日：2012-02-01
申请人： Kenji Aiko , Shigeya Tanaka , Yasuko Aoki , Hiroshi Kawaguchi , Kei Shimura
发明人： Kenji Aiko , Shigeya Tanaka , Yasuko Aoki , Hiroshi Kawaguchi , Kei Shimura
IPC分类号： G01N21/88 , G01B11/30 , G01N21/3581 , G01N21/94 , H01M4/04 , H01M4/139 , G01N21/3563
CPC分类号： G01N21/88 , G01B11/303 , G01N21/3563 , G01N21/3581 , G01N21/8806 , G01N21/94 , H01M4/0404 , H01M4/139 , Y02E60/122
摘要： The present invention provides a device for detecting foreign matter and a method for detecting foreign matter to detect a foreign matter on a surface of an object such as a film of an electrode mixture etc. or a foreign matter contained in the object, thereby to improve the reliability of the object. By irradiating an object with a terahertz illumination light 100 (wavelength of 4 μm to 10 mm) and detecting a scattered light 660 from an electrode 10 as an example of the object by a scattered light detector 200, a foreign matter on a surface of the electrode 10 or contained in the electrode 10, for example, a metal foreign matter 720, is detected. The electrode 10 is one in which electrode mixture layers 700 each including an active material 701, conductive additive and a binder as components are coated on both surfaces of a collector 710. The scattered light 660 results from a part of a transmitted light 656 reflected by the metal foreign matter 720.
摘要翻译：本发明提供一种检测异物的装置和检测异物以检测诸如电极混合物等的膜或物体中包含的异物的物体的表面上的异物的方法，从而改善对象的可靠性。通过用太赫兹照明光100（波长4μm〜10mm）照射物体，并通过散射光检测器200从作为物体的一个例子的电极10检测散射光660，检测电极10中或容纳在电极10中的金属异物720。电极10是其中各自包含活性材料701，导电添加剂和作为组分的粘合剂的电极混合物层700涂覆在集电体710的两个表面上的。散射光660由透射光656的一部分反射，金属异物720。

26. 发明授权

US07999565B2 Inspection apparatus and inspection method using electron beam 有权
标题翻译：使用电子束的检查装置和检查方法
公开(公告)号：US07999565B2
公开(公告)日：2011-08-16
申请号：US12348586
申请日：2009-01-05
申请人： Yasuhiro Gunji , Hiroshi Miyai , Shigeya Tanaka
发明人： Yasuhiro Gunji , Hiroshi Miyai , Shigeya Tanaka
IPC分类号： G01R31/305
CPC分类号： G01N23/203 , G01N23/2251 , G01N2223/3302 , H01J37/265 , H01J37/28 , H01J2237/2817
摘要： A visual inspection apparatus and method using the scanning electron microscope are disclosed. An electron beam is scanned repeatedly on a sample, and an inspection and a reference image are generated by the secondary electrons generated from the sample or reflected electrons. From the differential image between the inspection image and the reference image, a defect is determined. The number of pixels in the generated image along the direction of repetitive scanning by the electron beam can be changed.
摘要翻译：公开了使用扫描电子显微镜的目视检查装置和方法。在样品上重复扫描电子束，并且由从样品或反射电子产生的二次电子产生检查和参考图像。根据检查图像与参考图像之间的差分图像，确定缺陷。可以改变沿电子束的重复扫描方向产生的图像中的像素数。

27. 发明申请

US20080285841A1 IMAGE PROCESSING UNIT FOR WAFER INSPECTION TOOL 有权
标题翻译：用于检测工具的图像处理单元
公开(公告)号：US20080285841A1
公开(公告)日：2008-11-20
申请号：US12170532
申请日：2008-07-10
申请人： Michio NAKANO , Shigeya Tanaka , Yoshiyuki Momiyama , Takashi Hiroi , Kazuya Hayashi , Dai Fujii , Takako Fujisawa , Atsushi Ichige , Ichiro Kawashima
发明人： Michio NAKANO , Shigeya Tanaka , Yoshiyuki Momiyama , Takashi Hiroi , Kazuya Hayashi , Dai Fujii , Takako Fujisawa , Atsushi Ichige , Ichiro Kawashima
IPC分类号： G06K9/46
CPC分类号： G06T7/001 , G06T2200/28 , G06T2207/30148
摘要： An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.
摘要翻译：一种用于晶片检查工具的图像处理装置，其能够执行连续的单元到单元比较检查，管芯到管芯比较检查，以及使用多个处理器的单元到单元和管芯到管芯之间的混合比较检查。这种晶片检查工具的图像处理装置包括用于执行并行处理的多个处理器，用于在分区边界处切出包括前端重叠和后端重叠的图像数据的装置，以便将串行数据切割成预定图像尺寸用于将剪切图像数据分配给多个处理器，以及用于组装由多个处理器执行的处理结果的装置。前端重叠被设定为大于细胞对细胞比较检查的细胞的间距。

28. 发明授权

US07240159B2 Data processor having cache memory 失效
标题翻译：数据处理器具有高速缓冲存储器
公开(公告)号：US07240159B2
公开(公告)日：2007-07-03
申请号：US11014885
申请日：2004-12-20
申请人： Takashi Hotta , Toshihiko Kurihara , Shigeya Tanaka , Hideo Sawamoto , Akiyoshi Osumi , Koji Saito , Kotaro Shimamura
发明人： Takashi Hotta , Toshihiko Kurihara , Shigeya Tanaka , Hideo Sawamoto , Akiyoshi Osumi , Koji Saito , Kotaro Shimamura
IPC分类号： G06F12/02
CPC分类号： G06F12/0897 , G06F12/0846 , G06F12/0862 , G06F12/0864 , G06F2212/6028
摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.
摘要翻译：数据处理器具有大容量的第一高速缓冲存储器和一个端口，具有小容量的第二缓存存储器和设置在主存储器和指令处理部件之间的两个端口。经常使用的数据被存储在第一高速缓冲存储器中，并且在响应于预取指令的控制器的控制下，较不频繁使用的数据被存储在第二高速缓冲存储器中。高速缓存存储器中的一个可以是由多个存储器芯片构成的组合的相关高速缓冲存储器，每个存储器芯片具有至少两个存储器组，以及输出部分，以连续地访问数据集，并且一个在存储器组内一次。基于从指令处理部分发送的地址，选择存储体，并且将从所选择的存储体组中提取的数据提供给处理部分。

29. 发明授权

US6032229A Semiconductor memory device and information processor using the same 失效
标题翻译：半导体存储器件和信息处理器使用它
公开(公告)号：US6032229A
公开(公告)日：2000-02-29
申请号：US562187
申请日：1995-11-22
申请人： Takashi Hotta , Hideo Sawamoto , Noboru Akiyama , Takashi Akioka , Shigeya Tanaka
发明人： Takashi Hotta , Hideo Sawamoto , Noboru Akiyama , Takashi Akioka , Shigeya Tanaka
IPC分类号： G06F12/00 , G06F12/08 , G11C11/401 , G11C11/407 , G06F13/00
CPC分类号： G06F12/0855
摘要： An information processor having a high performance as a whole is provided by improving the throughput of the processor and the semiconductor memory device. The information processor comprises a memory having a buffer for temporarily holding data and a processor having a memory interface part for controlling the memory to transfer data to the buffer before determining whether the data is to be written in the memory and to write the data in said memory after determining of writing. Data writing and reading to the semiconductor device is pipelined by justifying data exchange between reading and writing. Since the data transfer timings of reading from a memory and writing in the memory can be executed at the same time, the reading process and the writing process can be performed by pipeline-like process and the throughput can be improved.
摘要翻译：通过提高处理器和半导体存储器件的吞吐量来提供整体上具有高性能的信息处理器。信息处理器包括具有用于临时保存数据的缓冲器的存储器和具有存储器接口部分的处理器，该存储器接口部分用于在确定数据是否被写入存储器之前控制存储器将数据传送到缓冲器，并将数据写入所述存储器记忆确定写作后。通过调整阅读和写入之间的数据交换，对半导体器件的数据写入和读取进行流水线化。由于可以同时执行从存储器的读取和写入的数据传送定时，因此可以通过流水线的处理来执行读取处理和写入处理，并且可以提高吞吐量。

30. 发明授权

US5590361A Microprocessor having an effective BiCMOS extra multiple input complex logic circuit 失效
标题翻译：微处理器具有有效的BiCMOS多输入复数逻辑电路
公开(公告)号：US5590361A
公开(公告)日：1996-12-31
申请号：US364406
申请日：1994-12-23
申请人： Masahiro Iwamura , Tatsumi Yamauchi , Shigeya Tanaka , Kazutaka Mori
发明人： Masahiro Iwamura , Tatsumi Yamauchi , Shigeya Tanaka , Kazutaka Mori
IPC分类号： H01L21/8249 , G06F15/16 , G06F15/78 , H01L27/06 , H03K19/08 , G06F15/00
CPC分类号： G06F15/7846 , Y02B60/1225
摘要： An extra large number-of-input complex logic circuit, employed inside a microprocessor for performing a large number of controls and arithmetic operations, is constructed utilizing N(N.gtoreq.2) number of a unit logic circuit each comprising M(M.gtoreq.1) input CMOS logic circuits and one bipolar transistor, whereby respective outputs are integrated to produce one output in response to M.times.N number input signals to provide a high speed, high density integration and low power consumption microprocessor.
摘要翻译：使用N（N> / = 2）个单元逻辑电路构造的微处理器中用于执行大量控制和算术运算的额外大量的输入复数逻辑电路，每个单元逻辑电路包括M（M> / = 1）输入CMOS逻辑电路和一个双极晶体管，由此各个输出被集成以响应于M×N个数字输入信号产生一个输出，以提供高速，高密度集成和低功耗微处理器。

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