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21. 发明申请

US20110108990A1 Capping of Copper Interconnect Lines in Integrated Circuit Devices 有权
标题翻译：集成电路器件中铜互连线的封盖
公开(公告)号：US20110108990A1
公开(公告)日：2011-05-12
申请号：US12613551
申请日：2009-11-06
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , David L. Rath , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , Chih-Chao Yang
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , David L. Rath , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , Chih-Chao Yang
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76849 , H01L21/76865 , H01L2924/0002 , H01L2924/00
摘要： A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.
摘要翻译：一种封盖线的方法包括通过选择性沉积工艺在铜线上形成金属膜层，铜线设置在电介质基底中，其中沉积还导致杂散金属材料沉积在介质基片的表面上，并用各向同性蚀刻工艺进行蚀刻以除去电介质基底表面上的金属膜层和杂散金属材料的一部分，其中金属膜层以足以使金属膜层盖保持在其上的初始厚度沉积铜线除去杂散金属材料。

22. 发明授权

US07563704B2 Method of forming an interconnect including a dielectric cap having a tensile stress 有权
标题翻译：形成包括具有拉伸应力的电介质盖的互连的方法
公开(公告)号：US07563704B2
公开(公告)日：2009-07-21
申请号：US11162666
申请日：2005-09-19
申请人： Chih-Chao Yang , Kaushik Chanda , Lawrence A. Clevenger , Yun-Yu Wang , Daewon Yang
发明人： Chih-Chao Yang , Kaushik Chanda , Lawrence A. Clevenger , Yun-Yu Wang , Daewon Yang
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76832 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and method of making the same are provided. The interconnect structure includes a dielectric layer having a patterned opening, a metal feature disposed in the patterned opening, and a dielectric cap overlying the metal feature. The dielectric cap has an internal tensile stress, the stress helping to avoid electromigration from occurring in a direction away from the metal line, especially when the metal line has tensile stress.
摘要翻译：提供了互连结构及其制造方法。互连结构包括具有图案化开口的电介质层，设置在图案化开口中的金属特征以及覆盖金属特征的电介质盖。电介质盖具有内部拉伸应力，该应力有助于避免在远离金属线的方向上发生电迁移，特别是当金属线具有拉伸应力时。

23. 发明授权

US07479869B2 Metal resistor and resistor material 失效
标题翻译：金属电阻和电阻材料
公开(公告)号：US07479869B2
公开(公告)日：2009-01-20
申请号：US11869218
申请日：2007-10-09
申请人： Chih-Chao Yang , Kaushik Chanda , Shyng-Tsong Chen
发明人： Chih-Chao Yang , Kaushik Chanda , Shyng-Tsong Chen
IPC分类号： H01C1/012
CPC分类号： H01L29/86 , H01L23/5228 , H01L2924/0002 , H04W36/08 , H04W88/08 , H04W88/18 , H01L2924/00
摘要： A metal resistor and resistor material are disclosed. The metal resistor may include an infused metal selected from the group consisting of: copper (Cu) infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W), and aluminum infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W). The resistor material may include one of: copper (Cu) infused with at least one of silicon (Si), nitrogen (2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W), and aluminum infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W).
摘要翻译：公开了一种金属电阻器和电阻器材料。金属电阻器可以包括从由以下组成的组中输入的输入金属：铜（Cu），其输入硅（Si），氮（N 2），碳（C），钽（Ta），钛（Ti）和钨（W）和铝（Si），氮（N 2），碳（C），钽（Ta），钛（Ti）和钨（W））中的至少一种的铝。电阻材料可以包括以下之一：用硅（Si），氮（2），碳（C），钽（Ta），钛（Ti）和钨（W）中的至少一种注入的铜（Cu）注入硅（Si），氮（N2），碳（C），钽（Ta），钛（Ti）和钨（W））中的至少一种。

24. 发明申请

US20080231312A1 Structure for modeling stress-induced degradation of conductive interconnects 失效
标题翻译：用于建模导电互连的应力诱导退化的结构
公开(公告)号：US20080231312A1
公开(公告)日：2008-09-25
申请号：US12154304
申请日：2008-05-22
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.
摘要翻译：提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平延伸平面该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。下导电或半导体元件可以与下通孔的底端接触。上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

25. 发明申请

US20120228770A1 METAL CAP FOR BACK END OF LINE (BEOL) INTERCONNECTS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE 有权
公开(公告)号：US20120228770A1
公开(公告)日：2012-09-13
申请号：US13474916
申请日：2012-05-18
申请人： Chih-Chao Yang , Kaushik Chanda , Daniel C. Edelstein
发明人： Chih-Chao Yang , Kaushik Chanda , Daniel C. Edelstein
IPC分类号： H01L23/482 , B82Y99/00
CPC分类号： H01L23/5329 , H01L21/76846 , H01L21/76849 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous.

26. 发明申请

US20120171860A1 METAL CAP FOR BACK END OF LINE (BEOL) INTERCONNECTS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE 有权
标题翻译：线束（BEOL）互连金属盖，设计结构和制造方法
公开(公告)号：US20120171860A1
公开(公告)日：2012-07-05
申请号：US13418659
申请日：2012-03-13
申请人： Chih-Chao Yang , Kaushik Chanda , Daniel C. Edelstein
发明人： Chih-Chao Yang , Kaushik Chanda , Daniel C. Edelstein
IPC分类号： H01L21/768
CPC分类号： H01L23/5329 , H01L21/76846 , H01L21/76849 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous.
摘要翻译：一种结构设置有用于后端线（BEOL）互连的金属盖，其基本上消除了电迁移（EM）损伤，设计结构和制造IC的方法。该结构包括形成在电介质材料中的金属互连和对金属互连有选择性的金属帽。金属盖包括RuX，其中X在硼，磷或硼和磷的组合。

27. 发明授权

US07955971B2 Hybrid metallic wire and methods of fabricating same 失效
标题翻译：混合金属线及其制造方法
公开(公告)号：US07955971B2
公开(公告)日：2011-06-07
申请号：US12482777
申请日：2009-06-11
申请人： Chih-Chao Yang , Kaushik Chanda , Daniel Edelstein , Baozhen Li
发明人： Chih-Chao Yang , Kaushik Chanda , Daniel Edelstein , Baozhen Li
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76846 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A structure and methods of fabricating the structure. The structure comprising: a trench in a dielectric layer; an electrically conductive liner, an electrically conductive core conductor and an electrically conductive fill material filling voids between said liner and said core conductor.
摘要翻译：一种制造结构的结构和方法。该结构包括：介电层中的沟槽; 导电衬垫，导电芯导体和填充所述衬套和所述芯导体之间的空隙的导电填充材料。

28. 发明授权

US07830019B2 Via bottom contact and method of manufacturing same 有权
标题翻译：通过底部接触及其制造方法
公开(公告)号：US07830019B2
公开(公告)日：2010-11-09
申请号：US12431289
申请日：2009-04-28
申请人： Kaushik Chanda , Lawrence A. Clevenger , Andrew P. Cowley , Jason P. Gill , Baozhen Li , Chih-Chao Yang
发明人： Kaushik Chanda , Lawrence A. Clevenger , Andrew P. Cowley , Jason P. Gill , Baozhen Li , Chih-Chao Yang
IPC分类号： H01L23/04
CPC分类号： H01L21/76865 , H01L21/76805 , H01L21/76846 , H01L21/76886
摘要： A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.
摘要翻译：制造器件的方法包括在形成在衬底和布线层中的蚀刻沟槽中沉积电迁移（EM）电阻材料。 EM电阻材料形成为与下面的扩散阻挡层和布线层电接触。该方法还包括形成与EM电阻材料和布线层电接触的通孔结构。该方法产生防止开路的结构。

29. 发明授权

US07745282B2 Interconnect structure with bi-layer metal cap 失效
标题翻译：互连结构与双层金属盖
公开(公告)号：US07745282B2
公开(公告)日：2010-06-29
申请号：US11675705
申请日：2007-02-16
申请人： Chih-Chao Yang , Kaushik Chanda , Ping-Chuan Wang
发明人： Chih-Chao Yang , Kaushik Chanda , Ping-Chuan Wang
IPC分类号： H01L21/8242 , H01L21/4763 , H01L21/22 , H01L21/38
CPC分类号： H01L21/76849 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76856 , H01L21/76883 , H01L21/76885 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of fabricating an interconnect structures with bi-layer metal cap is provided. In one embodiment, the method includes forming an interconnect feature in a dielectric material layer; and forming a bi-layer metallic cap on a top surface of the interconnect feature. The method further includes depositing a blanket layer of a dielectric capping layer, wherein the depositing covers an exposed surface of the dielectric material layer and a surface of the bi-layer metallic cap. The bi-layer metallic cap includes a metal capping layer formed on a conductive surface of the interconnect feature; and a metal nitride formed on a top portion of the metal capping layer. An interconnect structure is also described having an interconnect feature formed in a dielectric layer; a bi-layer metallic cap formed on a top portion of the interconnect feature; and a dielectric capping layer formed over the bi-layer metallic cap.
摘要翻译：提供了制造具有双层金属盖的互连结构的结构和方法。在一个实施例中，该方法包括在电介质材料层中形成互连特征; 以及在所述互连特征的顶表面上形成双层金属帽。该方法还包括沉积介电覆盖层的覆盖层，其中沉积覆盖电介质材料层的暴露表面和双层金属帽的表面。双层金属盖包括形成在互连特征的导电表面上的金属覆盖层; 以及形成在金属覆盖层的顶部上的金属氮化物。还描述了具有形成在电介质层中的互连特征的互连结构; 形成在互连特征的顶部上的双层金属帽; 以及形成在双层金属盖上的电介质覆盖层。

30. 发明申请

US20090200673A1 VIA BOTTOM CONTACT AND METHOD OF MANUFACTURING SAME 有权
标题翻译：通过底部接触及其制造方法
公开(公告)号：US20090200673A1
公开(公告)日：2009-08-13
申请号：US12431289
申请日：2009-04-28
申请人： Kaushik Chanda , Lawrence A. Clevenger , Andrew P. Cowley , Jason P. Gill , Baozhen Li , Chih-Chao Yang
发明人： Kaushik Chanda , Lawrence A. Clevenger , Andrew P. Cowley , Jason P. Gill , Baozhen Li , Chih-Chao Yang
IPC分类号： H01L23/532 , H01L23/48
CPC分类号： H01L21/76865 , H01L21/76805 , H01L21/76846 , H01L21/76886
摘要： A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.
摘要翻译：制造器件的方法包括在形成在衬底和布线层中的蚀刻沟槽中沉积电迁移（EM）电阻材料。 EM电阻材料形成为与下面的扩散阻挡层和布线层电接触。该方法还包括形成与EM电阻材料和布线层电接触的通孔结构。该方法产生防止开路的结构。

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