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21. 发明授权

US06673704B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06673704B2
公开(公告)日：2004-01-06
申请号：US10189598
申请日：2002-07-08
申请人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
发明人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
IPC分类号： H01L2140
CPC分类号： H01L21/76867 , H01L21/2855 , H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76859 , H01L21/76864 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L21/76889
摘要： A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在具有布线层的Si衬底上形成绝缘膜，形成与布线层连接的接触孔和绝缘膜中的布线槽，用Si 膜，依次在基板上形成Al膜和Ti膜，进行热处理，从而将Al膜替代为Ti膜，并使Si膜被Ti膜吸收，由此填充接触孔和Al膜的布线槽，除去由Ti膜和多余Ti吸收Si膜形成的由Ti硅化物构成的Ti / Ti硅化物，由此用Al塞填充接触孔，并填充布线槽与Al接线。

22. 发明授权

US06440843B1 Semiconductor device and method for manufacturing the same 失效
公开(公告)号：US06440843B1
公开(公告)日：2002-08-27
申请号：US09556961
申请日：2000-04-21
申请人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
发明人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
IPC分类号： H01L2358
CPC分类号： H01L21/76867 , H01L21/2855 , H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76859 , H01L21/76864 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L21/76889
摘要： A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

23. 发明授权

US07750473B2 LSI wiring pattern for reduced deformation and cracking 失效
标题翻译： LSI布线图案，减少变形和开裂
公开(公告)号：US07750473B2
公开(公告)日：2010-07-06
申请号：US11960209
申请日：2007-12-19
申请人： Takamasa Usui , Hideki Shibata , Tadashi Murofushi , Masakazu Jimbo , Hiroshi Hirayama
发明人： Takamasa Usui , Hideki Shibata , Tadashi Murofushi , Masakazu Jimbo , Hiroshi Hirayama
IPC分类号： H01L23/48
CPC分类号： H01L23/5222 , H01L23/522 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device including first and second wiring layers, and dummy and conductive patterns. The first and second wiring layers each have a hollow structure, and are stacked vertically adjacent to each other on a semiconductor substrate. The dummy pattern is formed in the first wiring layer, and does not function as a signal line. The conductive pattern is formed in the second wiring layer. The dummy and conductive patterns have an overlapping portion where these patterns overlap each other, and a non-overlapping portion where these patterns overlap each other, as viewed from above the semiconductor substrate.
摘要翻译：提供了包括第一和第二布线层以及虚拟和导电图案的半导体器件。第一和第二布线层各自具有中空结构，并且在半导体衬底上彼此垂直地堆叠。虚设图案形成在第一布线层中，不用作信号线。导电图案形成在第二布线层中。伪距和导电图案具有这些图案彼此重叠的重叠部分，以及从半导体基板的上方观察这些图案彼此重叠的非重叠部分。

24. 发明授权

US6071810A Method of filling contact holes and wiring grooves of a semiconductor device 失效
标题翻译：填充半导体器件的接触孔和布线槽的方法
公开(公告)号：US6071810A
公开(公告)日：2000-06-06
申请号：US997328
申请日：1997-12-23
申请人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
发明人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
IPC分类号： H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76867 , H01L21/2855 , H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76859 , H01L21/76864 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L21/76889
摘要： A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在具有布线层的Si衬底上形成绝缘膜，形成与布线层连接的接触孔和绝缘膜中的布线槽，用Si 膜，依次在基板上形成Al膜和Ti膜，进行热处理，从而将Al膜替代为Ti膜，并使Si膜被Ti膜吸收，由此填充接触孔和Al膜的布线槽，除去由Ti膜和多余Ti吸收Si膜形成的由Ti硅化物构成的Ti / Ti硅化物，由此用Al塞填充接触孔，并填充布线槽与Al接线。

25. 发明授权

US5759915A Method of forming semiconductor device having an improved buried electrode formed by selective CVD 失效
标题翻译：形成具有通过选择性CVD形成的改进的掩埋电极的半导体器件的方法
公开(公告)号：US5759915A
公开(公告)日：1998-06-02
申请号：US749379
申请日：1996-11-06
申请人： Noriaki Matsunaga , Hideki Shibata , Tadashi Matsuno , Takamasa Usui
发明人： Noriaki Matsunaga , Hideki Shibata , Tadashi Matsuno , Takamasa Usui
IPC分类号： H01L21/285 , H01L21/28 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76877
摘要： The present invention provides a semiconductor device including an improved buried electrode formed by selective CVD. In this semiconductor device, a first insulation layer is formed on a semiconductor substrate. A first conductive layer is formed along an inner surface of a recess of an opening formed on the first insulation layer. A second conductive layer is formed on the first conductive layer in the recess of the opening. The second conductive layer is flush with the first insulation layer. The surfaces of the first and second conductive layers are coated with a third conductive layer. A second insulation layer is formed on the first insulation layer and the third conductive layer. A via hole is formed through the second insulation layer and the third conductive layer and reaches to the second conductive layer. A buried electrode layer is grown in the via hole and formed in contact with the second conductive layer. A fourth insulation layer has a group of conductive layers formed on the second insulation layer and the buried electrode layer and electrically connected to the second conductive layer through the buried electrode layer formed in the via hole.
摘要翻译：本发明提供一种包括通过选择性CVD形成的改进的掩埋电极的半导体器件。在该半导体器件中，在半导体衬底上形成第一绝缘层。沿着形成在第一绝缘层上的开口的凹部的内表面形成第一导电层。在开口的凹部中的第一导电层上形成第二导电层。第二导电层与第一绝缘层齐平。第一和第二导电层的表面涂覆有第三导电层。在第一绝缘层和第三导电层上形成第二绝缘层。通过第二绝缘层和第三导电层形成通孔并到达第二导电层。掩埋电极层生长在通孔中并形成为与第二导电层接触。第四绝缘层具有形成在第二绝缘层和埋电极层上的一组导电层，并且通过形成在通孔中的掩埋电极层与第二导电层电连接。

26. 发明授权

US07875976B2 Semiconductor device including a silicide layer and a dielectric layer 有权
标题翻译：包括硅化物层和电介质层的半导体器件
公开(公告)号：US07875976B2
公开(公告)日：2011-01-25
申请号：US11868011
申请日：2007-10-05
申请人： Makoto Wada , Takamasa Usui , Kazuya Ohuchi
发明人： Makoto Wada , Takamasa Usui , Kazuya Ohuchi
IPC分类号： H01L23/52
CPC分类号： H01L23/485 , H01L21/76831 , H01L21/76843 , H01L21/76858 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L2924/0002 , H01L2924/00
摘要： In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, a silicide layer provided on the semiconductor substrate, a dielectric layer provided on the semiconductor substrate, a contact layer provided on the silicide layer, a metal layer provided in the dielectric layer and electrically connected to the silicide layer via the contact layer, a diffusion barrier layer provided between the dielectric layer and the metal layer, wherein the contact layer includes a first metal element provided in the metal layer, a second metal element provided in the diffusion barrier layer and at least one of a third metal provided in the silicide layer and Si element.
摘要翻译：在本发明的一个方面中，半导体器件可以包括半导体衬底，设置在半导体衬底上的硅化物层，设置在半导体衬底上的电介质层，设置在硅化物层上的接触层，设置在该半导体衬底上的金属层电介质层，经由接触层与硅化物层电连接，设置在介电层和金属层之间的扩散阻挡层，其中接触层包括设置在金属层中的第一金属元件，设置在金属层中的第二金属元件扩散阻挡层和设置在硅化物层和Si元件中的第三金属中的至少一个。

27. 发明申请

US20080088021A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：US20080088021A1
公开(公告)日：2008-04-17
申请号：US11868011
申请日：2007-10-05
申请人： Makoto WADA , Takamasa Usui , Kazuya Ohuchi
发明人： Makoto WADA , Takamasa Usui , Kazuya Ohuchi
IPC分类号： H01L23/532 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/76831 , H01L21/76843 , H01L21/76858 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L2924/0002 , H01L2924/00
摘要： In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, a silicide layer provided on the semiconductor substrate, a dielectric layer provided on the semiconductor substrate, a contact layer provided on the silicide layer, a metal layer provided in the dielectric layer and electrically connected to the silicide layer via the contact layer, a diffusion barrier layer provided between the dielectric layer and the metal layer, wherein the contact layer includes a first metal element provided in the metal layer, a second metal element provided in the diffusion barrier layer and at least one of a third metal provided in the silicide layer and Si element.
摘要翻译：在本发明的一个方面中，半导体器件可以包括半导体衬底，设置在半导体衬底上的硅化物层，设置在半导体衬底上的电介质层，设置在硅化物层上的接触层，设置在该半导体衬底上的金属层电介质层，经由接触层与硅化物层电连接，设置在介电层和金属层之间的扩散阻挡层，其中接触层包括设置在金属层中的第一金属元件，设置在金属层中的第二金属元件扩散阻挡层和设置在硅化物层和Si元件中的第三金属中的至少一个。

28. 发明授权

US08456186B2 Reliability evaluation test apparatus, reliability evaluation test system, contactor, and reliability evaluation test method 失效
标题翻译：可靠性评估试验装置，可靠性评价试验系统，接触器和可靠性评价试验方法
公开(公告)号：US08456186B2
公开(公告)日：2013-06-04
申请号：US11769432
申请日：2007-06-27
申请人： Kiyoshi Takekoshi , Hisatomi Hosaka , Junichi Hagihara , Kunihiko Hatsushika , Takamasa Usui , Hisashi Kaneko , Nobuo Hayasaka , Yoshiyuki Ido
发明人： Kiyoshi Takekoshi , Hisatomi Hosaka , Junichi Hagihara , Kunihiko Hatsushika , Takamasa Usui , Hisashi Kaneko , Nobuo Hayasaka , Yoshiyuki Ido
IPC分类号： G01R31/02 , G01R31/00
CPC分类号： G01R31/2862 , G01R1/0433 , G01R1/0491 , G01R31/2831 , G01R31/286 , G01R31/2865 , G01R31/2867 , G01R31/287 , G01R31/2886
摘要： A reliability evaluation test apparatus of this invention includes a wafer storage section which stores a wafer in a state wherein the electrode pads of a number of devices formed on the wafer and the bumps of a contactor are totally in electrical contact with each other. The wafer storage section transmits/receives a test signal to/from a measurement section and has a hermetic and heat insulating structure. The wafer storage section has a pressure mechanism which presses the contactor and a heating mechanism which directly heats the wafer totally in contact with the contactor to a predetermined high temperature. The reliability of an interconnection film and insulating film formed on the semiconductor wafer are evaluated under an accelerated condition.
摘要翻译：本发明的可靠性评价试验装置包括晶片存储部，其以形成在晶片上的多个器件的电极焊盘和接触器的凸块完全电接触的状态存储晶片。晶片存储部分向/从测量部分发送/接收测试信号，并具有密封和隔热结构。晶片存储部分具有压力接触器的压力机构和将与接触器完全接触的晶片直接加热到预定高温的加热机构。在加速条件下评估形成在半导体晶片上的互连膜和绝缘膜的可靠性。

29. 发明授权

US08454135B2 Air bubble removal in an ink jet printer 有权
标题翻译：喷墨打印机中的气泡去除
公开(公告)号：US08454135B2
公开(公告)日：2013-06-04
申请号：US12071787
申请日：2008-02-26
申请人： Takaichiro Umeda , Hikaru Kaga , Tsuyoshi Suzuki , Seiji Shimizu , Takamasa Usui , Yoichiro Shimizu
发明人： Takaichiro Umeda , Hikaru Kaga , Tsuyoshi Suzuki , Seiji Shimizu , Takamasa Usui , Yoichiro Shimizu
IPC分类号： B41J2/17 , B41J2/19
CPC分类号： B41J2/17513 , B41J2/17523 , B41J2/17556
摘要： An ink jet printer including a carriage which is movable relative to a sheet of paper, a recording head which is mounted on the carriage and records an image on the sheet by ejecting a droplet of ink toward the sheet, one or more ink tanks which store the ink or inks to be supplied to the recording head, a buffer tank which is mounted on the carriage, and one or more ink flow passages in which the inks are supplied from the ink tanks to the recording head via the buffer tank. The buffer tank has, at a height position higher than a height position where the recording head is provided, one or more air buffer chambers which accommodate respective amounts of the inks, and collect air bubbles produced in the ink flow passages.
摘要翻译：一种喷墨打印机，其包括可相对于一张纸移动的托架;记录头，其安装在托架上，并通过向纸张喷射墨滴将图像记录在纸张上;一个或多个墨盒，其存储要提供给记录头的墨水或墨水，安装在滑架上的缓冲罐，以及一个或多个墨水流动通道，其中墨水通过缓冲罐从墨水盒供应到记录头。缓冲罐在高于设置有记录头的高度位置的高度位置处具有一个或多个空气缓冲室，其适应相应量的油墨，并且收集在油墨流动通道中产生的气泡。

30. 发明授权

US07936070B2 Semiconductor device and method for fabricating semiconductor device 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07936070B2
公开(公告)日：2011-05-03
申请号：US12435485
申请日：2009-05-05
申请人： Yumi Hayashi , Noriaki Matsunaga , Takamasa Usui
发明人： Yumi Hayashi , Noriaki Matsunaga , Takamasa Usui
IPC分类号： H01L23/48
CPC分类号： H01L21/76846 , H01L21/76847 , H01L21/76849 , H01L21/76867 , H01L21/76877 , H01L21/76886 , H01L21/76888 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a copper (Cu) wire having a first region and a second region in which densities of silicon (Si) and oxygen (O) atoms are higher than in the first region; a compound film that is selectively formed on the Cu wire and contains Cu and Si; and a dielectric film formed on a side surface side of the Cu wire.
摘要翻译：半导体器件包括：铜（Cu）线，其具有第一区域和第二区域，其中硅（Si）和氧（O）原子的密度高于第一区域; 选择性地形成在Cu线上并含有Cu和Si的复合膜; 以及形成在Cu线的侧面侧的电介质膜。

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