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21. 发明授权

US5702977A Shallow trench isolation method employing self-aligned and planarized trench fill dielectric layer 失效
标题翻译：采用自对准和平面化沟槽填充介质层的浅沟槽隔离方法
公开(公告)号：US5702977A
公开(公告)日：1997-12-30
申请号：US810390
申请日：1997-03-03
申请人： Syun-Ming Jang , Ying-Ho Chen , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Chen-Hua Yu
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A method for forming within a trench within a substrate within an integrated circuit a planarized trench fill layer. There is first provided a substrate having a trench formed therein. There is formed upon the substrate at regions other than those within the trench a first integrated circuit layer which has a composition which inhibits formation upon the first integrated circuit layer of a trench fill layer which is subsequently formed upon the substrate and within the trench. There is also formed within the trench but not upon the substrate at regions other than those within the trench a second integrated circuit layer which has a composition which promotes formation within the trench of the trench fill layer which is subsequently formed upon the substrate and within the trench. Finally, there is formed upon the substrate and within the trench the trench fill layer. The trench fill layer is formed to a thickness over the trench such that when the trench fill layer is planarized through a chemical mechanical polish (CMP) planarizing method there is avoided formation of a dish within a planarized trench fill layer formed within the trench.
摘要翻译：一种在集成电路内的衬底内的沟槽内形成平坦化沟槽填充层的方法。首先提供其中形成有沟槽的衬底。在沟槽内的不同于沟槽内的区域的基底上形成第一集成电路层，该第一集成电路层具有阻止在沟槽填充层的第一集成电路层上形成的组成，后者形成在衬底上并在沟槽内。在沟槽内还形成在衬底上的不在沟槽内的衬底上的第二集成电路层，该第二集成电路层具有促进在沟槽填充层的沟槽内形成的组成，其随后形成在衬底上并在衬底内沟。最后，在衬底上并在沟槽内形成沟槽填充层。沟槽填充层形成为在沟槽上方的厚度，使得当沟槽填充层通过化学机械抛光（CMP）平面化方法平坦化时，避免在形成在沟槽内的平坦化沟槽填充层内形成皿。

22. 发明申请

US20060211250A1 Scratch reduction for chemical mechanical polishing 有权
标题翻译：化学机械抛光刮刮
公开(公告)号：US20060211250A1
公开(公告)日：2006-09-21
申请号：US11082517
申请日：2005-03-17
申请人： Chuang-Ping Hou , Syun-Ming Jang , Ying-Ho Chen , Chu-Yun Fu , Tung-Ching Tseng
发明人： Chuang-Ping Hou , Syun-Ming Jang , Ying-Ho Chen , Chu-Yun Fu , Tung-Ching Tseng
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/31053
摘要： A method for forming a semiconductor device utilizing a chemical-mechanical polishing (CMP) process is provided. In one example, the method includes sequentially performing a first CMP process for removing a first portion of an oxide surface of a semiconductor device using a high selectivity slurry (HSS) and a first polish pad, interrupting the first CMP process, cleaning the semiconductor device and the first polish pad, and performing a second CMP process for removing a second portion of the oxide surface.
摘要翻译：提供了一种利用化学机械抛光（CMP）工艺形成半导体器件的方法。在一个示例中，该方法包括依次执行第一CMP处理，以使用高选择性浆料（HSS）和第一抛光垫去除半导体器件的氧化物表面的第一部分，中断第一CMP工艺，清洁半导体器件和第一抛光垫，并且执行用于去除氧化物表面的第二部分的第二CMP工艺。

23. 发明授权

US06736701B1 Eliminate broken line damage of copper after CMP 失效
标题翻译：消除CMP后的铜线损伤
公开(公告)号：US06736701B1
公开(公告)日：2004-05-18
申请号：US09989838
申请日：2001-11-20
申请人： Shau-Lin Shue , Ying-Ho Chen , Wen-Chih Chiou , Tsu Shih , Syun-Ming Jang
发明人： Shau-Lin Shue , Ying-Ho Chen , Wen-Chih Chiou , Tsu Shih , Syun-Ming Jang
IPC分类号： B24B100
CPC分类号： B24B37/042 , B24B21/04
摘要： A new method is provided for the post-deposition treatment of copper lines. A damascene copper line pattern whereby a TaN barrier layer and a seed layer have been provided is polished. Under the first embodiment of the invention, the deposited copper is polished (Cu CMP), the surface of the wafer is rinsed using a first High Flow DI rinse that contains a TBA inhibitor. The TaN CMP is performed immediately following the first High Flow DI rinse. A second High Flow DI rinse is applied using DI water that contains TBA inhibitor. The required following rinse step is executed immediately after the second High Flow DI rinse has been completed. Under the second embodiment of the invention, the process of CMP has been divided in two distinct steps where the first step is aimed at corrosion elimination and the second step is aimed at elimination of mechanical damage to the polished copper. The processing conditions for the second processing step have been extended and optimized, thereby using a second belt of a CMP apparatus.
摘要翻译：提供了一种新的铜线后处理方法。抛光已经提供TaN阻挡层和种子层的镶嵌铜线图案。在本发明的第一实施例中，抛光沉积的铜（Cu CMP），使用含有TBA抑制剂的第一高流量DI冲洗冲洗晶片的表面。在第一次高流量DI冲洗之后立即执行TaN CMP。使用含有TBA抑制剂的去离子水进行第二次高流量DI冲洗。第二次高流量DI冲洗完成后立即执行所需的冲洗步骤。在本发明的第二个实施方案中，CMP的方法分为两个不同的步骤，其中第一步骤旨在消除腐蚀，第二步骤旨在消除抛光铜的机械损伤。第二处理步骤的处理条件已被扩展和优化，从而使用CMP设备的第二带。

24. 发明授权

US06635211B2 Reinforced polishing pad for linear chemical mechanical polishing and method for forming 有权
公开(公告)号：US06635211B2
公开(公告)日：2003-10-21
申请号：US09888789
申请日：2001-06-25
申请人： Wen-Chih Chiou , Ying-Ho Chen , Tsu Shih , Syun-Ming Jang
发明人： Wen-Chih Chiou , Ying-Ho Chen , Tsu Shih , Syun-Ming Jang
IPC分类号： B29C3912
CPC分类号： B29C39/025 , B24B37/042 , B29C70/64 , B29C2793/009 , B29K2105/126 , B29K2105/128 , B29K2105/16 , B29L2031/709 , B29L2031/736
摘要： A continuous loop polishing pad that is reinforced by a reinforcing filler and a method for fabricating the polishing pad are described. The reinforced polishing pad is constructed by a sub-layer and a top layer, wherein the sub-layer defines an inner diameter of the polishing pad and contains a reinforcing filler with an aspect ratio of at least 10 oriented substantially in a circumferential direction of the continuous loop polishing pad. The top layer is laminated to the sub-layer with a top surface defining an outer diameter of the polishing pad, while both the sub-layer and the top layer are formed of a polymeric material. The invention further describes a method for fabricating the reinforced polishing pad in a continuous loop.

25. 发明授权

US06589872B1 Use of low-high slurry flow to eliminate copper line damages 有权
标题翻译：使用低 - 高泥浆流量来消除铜线损坏
公开(公告)号：US06589872B1
公开(公告)日：2003-07-08
申请号：US09304302
申请日：1999-05-03
申请人： Jih-Churng Twu , Ying-Ho Chen , Tsu Shih , Syun-Ming Jang
发明人： Jih-Churng Twu , Ying-Ho Chen , Tsu Shih , Syun-Ming Jang
IPC分类号： H01K2120
CPC分类号： B24B37/042 , B24B49/00 , B24B57/02
摘要： The invention teaches a new method of applying slurry during the process of chemical mechanical polishing of copper surfaces. By varying the rate of slurry deposition, starting out with a low rate of slurry flow that is increased as the polishing process proceeds, the invention obtains good planarity for copper surfaces while saving on the amount of slurry that is being used for the copper surface polishing process.
摘要翻译：本发明教导了在铜表面的化学机械抛光过程中施加浆料的新方法。通过改变浆料沉积速率，随着抛光工艺的进行，随着浆料流动速度的降低而开始，本发明对于铜表面获得了良好的平面性，同时节省了用于铜表面抛光的浆料量处理。

26. 发明授权

US06429118B1 Elimination of electrochemical deposition copper line damage for damascene processing 有权
标题翻译：消除电化学沉积铜线损坏镶嵌加工
公开(公告)号：US06429118B1
公开(公告)日：2002-08-06
申请号：US09664414
申请日：2000-09-18
申请人： Ying-Ho Chen , Syun-Ming Jang , Jih-Churng Twu , Tsu Shih
发明人： Ying-Ho Chen , Syun-Ming Jang , Jih-Churng Twu , Tsu Shih
IPC分类号： H01L213213
CPC分类号： H01L21/76802 , H01L21/2855 , H01L21/7684 , H01L21/76877
摘要： An improved and new process, used for the elimination of copper line damage in damacene processing, is disclosed. By depositing copper by physical vapor deposition (PVD), sputtering, preferably by an ion metal plasma (IMP) scheme or chemical vapor deposition (CVD), the deposited copper fills pinholes or intra-cracks (micro-cracks), caused by poor gap filling of purely electrochemical deposition of copper plating. By this process or method, chemical attack on copper lines, by chemicals in the subsequent chemical mechanical polish (CMP) back and post-cleaning steps, is prevented.
摘要翻译：公开了一种改进和新的方法，用于消除碲化氢处理中的铜线损伤。通过物理气相沉积（PVD），优选通过离子金属等离子体（IMP）方案或化学气相沉积（CVD）沉积铜，沉积的铜填充由差的间隙引起的针孔或裂纹（微裂纹）填充电镀纯电化学沉积。通过该方法或方法，可以防止化学品在后续的化学机械抛光（CMP）背面和后清洗步骤中对铜线进行化学侵蚀。

27. 发明授权

US06391777B1 Two-stage Cu anneal to improve Cu damascene process 有权
标题翻译：两级Cu退火以改善Cu镶嵌工艺
公开(公告)号：US06391777B1
公开(公告)日：2002-05-21
申请号：US09846481
申请日：2001-05-02
申请人： Ying-Ho Chen , Syun-Ming Jang
发明人： Ying-Ho Chen , Syun-Ming Jang
IPC分类号： H01L2144
CPC分类号： H01L21/7684 , H01L21/76877
摘要： A method is disclosed to improve the reliability of copper damascene interconnects. This is accomplished by performing a two-stage anneal of the copper metal; first, after the deposition of copper in the damascene, and then for the second time, after the removal of excess copper by chemical mechanical polishing.
摘要翻译：公开了一种提高铜镶嵌互连的可靠性的方法。这通过进行铜金属的两阶段退火来实现; 首先，在铜镶嵌后，然后再次通过化学机械抛光去除多余的铜。

28. 发明授权

US06383930B1 Method to eliminate copper CMP residue of an alignment mark for damascene processes 有权
标题翻译：消除用于镶嵌工艺的对准标记的铜CMP残留物的方法
公开(公告)号：US06383930B1
公开(公告)日：2002-05-07
申请号：US09902896
申请日：2001-07-12
申请人： Ying-Ho Chen , Wen-Chih Chiou , Tsu Shih , Syun-Ming Jang
发明人： Ying-Ho Chen , Wen-Chih Chiou , Tsu Shih , Syun-Ming Jang
IPC分类号： H01K2144
CPC分类号： H01L21/76885 , H01L21/7684 , H01L21/76877 , H01L23/544 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
摘要： A new method is provided that affects the polishing rate of the surface of a layer of copper, that has been deposited over the surface of a layer of dielectric. Copper damascene structures have been created in the surface of the layer of dielectric, the layer of dielectric also overlies an alignment mark. The surface of the layer of dielectric that is aligned with the alignment mark is provided with dummy damascene structures, assuring equal polishing rates for active damascene structures and the surface region of the layer of dielectric overlying an alignment mark.
摘要翻译：提供了一种新的方法，其影响已经沉积在电介质层的表面上的铜层的表面的抛光速率。在电介质层的表面已经形成铜镶嵌结构，电介质层也覆盖对准标记。与对准标记对准的电介质层的表面设置有虚拟镶嵌结构，确保活性镶嵌结构的相同抛光速率和覆盖对准标记的电介质层的表面区域。

29. 发明授权

US06197660B1 Integration of CMP and wet or dry etching for STI 有权
标题翻译：用于STI的CMP和湿法或干蚀刻的集成
公开(公告)号：US06197660B1
公开(公告)日：2001-03-06
申请号：US09301223
申请日：1999-04-29
申请人： Syun-Ming Jang , Ying-Ho Chen
发明人： Syun-Ming Jang , Ying-Ho Chen
IPC分类号： H01L2176
CPC分类号： H01L21/31111 , H01L21/31053 , H01L21/31055 , H01L21/31612 , H01L21/3185 , H01L21/76229
摘要： Shallow trench isolation in which trenches having varying dimensions have been formed in a hard surface such as silicon nitride can lead to dishing inside the larger trenches. To overcome this, the trenches were first over-filled with a layer of HDPCVD oxide followed by the deposition of a relatively soft dielectric layer, using a conformal deposition method. CMP was then used to remove both the added layer and most of the original HDPCVD oxide, a small thickness of the latter being left in place. Because of the earlier influence of the added layer the resulting surface was planar and a conventional wet or dry etch could be used to remove the remaining oxide, thereby exposing the top surface and fully filling the trenches without any dishing.
摘要翻译：浅沟槽隔离，其中具有不同尺寸的沟槽已经形成在诸如氮化硅的硬表面中，可能导致较大沟槽内的凹陷。为了克服这一点，首先用一层HDPCVD氧化物填充沟槽，然后使用共形沉积方法沉积相对软的介电层。然后使用CMP去除添加的层和大部分原始HDPCVD氧化物，后者的小厚度留在原位。由于添加层的早期影响，所得表面是平面的，并且可以使用常规的湿法或干法蚀刻来除去剩余的氧化物，从而暴露顶表面并完全填充沟槽而没有任何凹陷。

30. 发明授权

US6100163A Gap filling of shallow trench isolation by ozone-tetraethoxysilane 有权
标题翻译：通过臭氧四乙氧基硅烷进行浅沟隔离的间隙填充
公开(公告)号：US6100163A
公开(公告)日：2000-08-08
申请号：US226277
申请日：1999-01-07
申请人： Syun-Ming Jang , Ying-Ho Chen , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Chen-Hua Yu
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method for filling a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then oxidized thermally the silicon substrate to form within the trench a thermal silicon oxide trench liner layer. There is then treated the thermal silicon oxide trench liner layer by exposure to a plasma formed from a gas composition which upon plasma activation simultaneously supplies an active nitrogen containing species and an active oxygen containing species to form a plasma treated thermal silicon oxide trench liner layer. There is then formed upon the plasma treated thermal silicon oxide trench liner layer a conformal silicon oxide intermediate layer formed through a plasma enhanced chemical vapor deposition (PECVD) method employing a silane silicon source material. Finally, there is then formed upon the conformal silicon oxide intermediate layer a gap filling silicon oxide trench fill layer through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material.
摘要翻译：一种用于在硅衬底内填充沟槽的方法。首先提供其中形成有沟槽的硅衬底。然后将硅衬底热氧化以在沟槽内形成热氧化硅沟槽衬垫层。然后通过暴露于由气体组合物形成的等离子体来处理热氧化硅沟槽衬里层，其在等离子体激活时同时提供含活性氮的物质和含活性氧的物质以形成等离子体处理的热氧化硅沟槽衬里层。然后在等离子体处理的热氧化硅沟槽衬垫层上形成通过使用硅烷硅源材料的等离子体增强化学气相沉积（PECVD）方法形成的共形氧化硅中间层。最后，通过使用臭氧氧化剂和四乙基原硅酸盐的臭氧辅助亚大气压热化学气相沉积（SACVD）方法，在保形氧化硅中间层上形成填充氧化硅沟槽填充层的间隙（TEOS）硅源材料。

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