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21. 发明授权

US06574784B1 Short edge management in rule based OPC 有权
标题翻译：基于规则的OPC的边缘管理
公开(公告)号：US06574784B1
公开(公告)日：2003-06-03
申请号：US09882802
申请日：2001-06-14
申请人： George P. Lippincott , Kyohei Sakajiri , Laurence W. Grodd
发明人： George P. Lippincott , Kyohei Sakajiri , Laurence W. Grodd
IPC分类号： G06F945
CPC分类号： G06F17/5068 , G06F17/5081
摘要： The invention discloses a method and apparatus for modifying, as appropriate, the geometries of a polygon. Based on various attributes associated with the polygon and its surroundings, modification of the location of the edge segments may conditionally occur. Additionally, if these modifications occur, a method to minimize the introduction of short edges during the modification is provided.
摘要翻译：本发明公开了适当地修改多边形的几何形状的方法和装置。基于与多边形及其周围环境相关联的各种属性，可以有条件地发生边缘片段的位置的修改。此外，如果发生这些修改，则提供了在修改期间最小化引入短边缘的方法。

22. 发明授权

US06415421B1 Integrated verification and manufacturability tool 有权
公开(公告)号：US06415421B1
公开(公告)日：2002-07-02
申请号：US09747190
申请日：2000-12-22
申请人： Leigh C. Anderson , Nicolas B. Cobb , Laurence W. Grodd , Emile Sahouria , Siqiong You
发明人： Leigh C. Anderson , Nicolas B. Cobb , Laurence W. Grodd , Emile Sahouria , Siqiong You
IPC分类号： G06F1750
摘要： An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.

23. 发明授权

US4885714A Calculator having a user-accessible object stack for the uniform application of mathematical functions and logical operations to a multiplicity of object types 失效
标题翻译：计算器具有用户可访问对象堆栈，用于将数学函数和逻辑操作统一应用于多种对象类型
公开(公告)号：US4885714A
公开(公告)日：1989-12-05
申请号：US923933
申请日：1986-10-27
申请人： Gabe L. Eisenstein , Laurence W. Grodd , Paul J. McClellan , Robert M. Miller , Charles M. Patton , William C. Wickes
发明人： Gabe L. Eisenstein , Laurence W. Grodd , Paul J. McClellan , Robert M. Miller , Charles M. Patton , William C. Wickes
IPC分类号： G06F9/44 , G06F15/02
CPC分类号： G06F9/44 , G06F15/02
摘要： A calculator is defined by a user-interface centered around a last in first out stack of mathematical or logical objects, that is both visible and accessible to a user. Objects may be any of a number of different types, each type characterized by specific logical or mathematical rules. Calculator operations are provided that may be applied in a uniform manner to the objects, affecting either or both the internal composition of the objects or the external positions and number of the objects on the stack. Objects of different types are distinguished upon entry on the stack and in visible display by characteristic prefix and postfix symbols, and can be entered from a keyboard or created dynamically as the result of calculator operations.
摘要翻译：计算器由围绕数学或逻辑对象的最后一个堆栈的用户界面定义，这是用户可见和可访问的。对象可以是多种不同类型中的任何一种，每种类型以特定的逻辑或数学规则为特征。提供了可以以均匀的方式应用于对象的计算器操作，影响对象的内部组成或者堆叠上的对象的外部位置和数量。不同类型的对象在堆栈上进入并通过特征前缀和后缀符号进行可见显示时被区分，并且可以从键盘输入或作为计算器操作的结果动态创建。

24. 发明授权

US4821228A Method and apparatus for computation stack recovery in a calculator 失效
标题翻译：计算器中计算堆栈恢复的方法和装置
公开(公告)号：US4821228A
公开(公告)日：1989-04-11
申请号：US946543
申请日：1986-12-24
申请人： William C. Wickes , Laurence W. Grodd
发明人： William C. Wickes , Laurence W. Grodd
IPC分类号： G06F15/00 , G06F3/02 , G06F11/14 , G06F15/02 , G06F15/06 , G06F11/00
CPC分类号： G06F11/1415
摘要： A method and apparatus for recovery of a computation stack in a calculator is presented in accordance with a preferred embodiment of the present invention. In a calculator employing a stack for the storage of data to be utilized in a calculation, provision is made to store the contents of the stack before a calculation is performed. If, after the calculation is performed a user desires to "undo" the calculation, he may strike an "undo" key. The original state of the stack is then restored.

25. 发明授权

US09652574B2 Simultaneous multi-layer fill generation 有权
公开(公告)号：US09652574B2
公开(公告)日：2017-05-16
申请号：US13093828
申请日：2011-04-25
申请人： Eugene Anikin , Fedor G. Pikus , Laurence W. Grodd , David A. Abercrombie , John W. Stedman
发明人： Eugene Anikin , Fedor G. Pikus , Laurence W. Grodd , David A. Abercrombie , John W. Stedman
IPC分类号： G06F17/50 , G03F1/44 , H01L27/02
CPC分类号： G06F17/5072 , G03F1/44 , G06F17/5045 , G06F17/5068 , G06F2217/12 , H01L27/0207 , Y02P90/265
摘要： Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.

26. 发明申请

US20100223583A1 HIERARCHICAL FEATURE EXTRACTION FOR ELECTRICAL INTERACTION CALCULATIONS 有权
标题翻译：电力交互计算的分层特征提取
公开(公告)号：US20100223583A1
公开(公告)日：2010-09-02
申请号：US12777226
申请日：2010-05-10
申请人： Thomas H. Kauth , Patrick D. Gibson , Kurt C. Hertz , Laurence W. Grodd
发明人： Thomas H. Kauth , Patrick D. Gibson , Kurt C. Hertz , Laurence W. Grodd
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
摘要翻译：计算集成电路布局中的电路元件的电学相互作用的方法，而不使整个描述布局的数据库变平坦。在一个实施例中，分析分层数据库，并且在重复模式的每个实例处重新使用针对重复模式元素进行的电阻和电容计算，并根据局部条件进行调整。在另一个实施例中，将电路布局转换成多个瓦片，其中对瓦片的中心的电路元件和瓦片的边界区域进行的电阻和电容计算分别计算并组合。影响不同级别层次的电路元件之间的电气相互作用的环境信息是在较低级别的层次上进行计算，因此不需要对重复单元格的每个放置进行此类计算，因此不需要促进所有相互作用的元素到相同的层次级别来计算电相互作用。

27. 发明申请

US20080235497A1 Parallel Data Output 审中-公开
标题翻译：并行数据输出
公开(公告)号：US20080235497A1
公开(公告)日：2008-09-25
申请号：US11945263
申请日：2007-11-26
申请人： Jimmy J. Tomblin , Laurence W. Grodd , Robert A. Todd
发明人： Jimmy J. Tomblin , Laurence W. Grodd , Robert A. Todd
IPC分类号： G06F9/315
CPC分类号： G06F17/5068
摘要： Multiple processing threads operate in parallel to convert data, produced by one or more electronic design automation processes in an initial format, into another data format for output. A processing thread accesses a portion of the initial results data produced by one or more electronic design automation processes in an initial format and in an initial organizational arrangement. The processing thread will then store data within this portion of the initial results data belonging to a target category of the desired output organizational arrangement, such as a cell, at a memory location corresponding to that target category. It will also convert the stored data from a first data format to another data format for output. The first data format may use a relatively low amount of compression, with the second data format may use a relatively high level of compression. Each of a plurality of processing threads may operate in this manner in parallel upon portions of the initial results data, until all of the initial results data has been converted to the desired data format for output. A processing thread can then collect the converted data from the various memory locations, and provide it as output data for the electronic design automation process or processes.
摘要翻译：多个处理线程并行运行，将由一个或多个电子设计自动化过程产生的数据以初始格式转换成另一种数据格式进行输出。处理线程以初始格式和初始组织布置访问由一个或多个电子设计自动化处理产生的初始结果数据的一部分。然后，处理线程将在属于期望的输出组织布置的目标类别（例如单元）的初始结果数据的该部分内的数据存储在对应于该目标类别的存储器位置。它还将存储的数据从第一个数据格式转换为另一个数据格式进行输出。第一数据格式可以使用相对低的压缩量，第二数据格式可以使用相对较高的压缩级别。多个处理线程中的每一个可以以这种方式在初始结果数据的一部分上并行操作，直到所有的初始结果数据已被转换为期望的数据格式以供输出。然后，处理线程可以从各种存储器位置收集转换的数据，并将其提供为用于电子设计自动化过程或过程的输出数据。

28. 发明授权

US07181721B2 Short edge management in rule based OPC 有权
标题翻译：基于规则的OPC的边缘管理
公开(公告)号：US07181721B2
公开(公告)日：2007-02-20
申请号：US10873589
申请日：2004-06-22
申请人： George P. Lippincott , Kyohei Sakajiri , Laurence W. Grodd
发明人： George P. Lippincott , Kyohei Sakajiri , Laurence W. Grodd
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081
摘要： The invention discloses a method and apparatus for modifying, as appropriate, the geometries of a polygon. Based on various attributes associated with the polygon and its surroundings, modification of the location of the edge segments may conditionally occur. Additionally, if these modifications occur, a method to minimize the introduction of short edges during the modification is provided.
摘要翻译：本发明公开了适当地修改多边形的几何形状的方法和装置。基于与多边形及其周围环境相关联的各种属性，可以有条件地发生边缘片段的位置的修改。此外，如果发生这些修改，则提供了在修改期间最小化引入短边缘的方法。

29. 发明授权

US07017141B2 Integrated verification and manufacturability tool 有权
公开(公告)号：US07017141B2
公开(公告)日：2006-03-21
申请号：US10112223
申请日：2002-03-27
申请人： Leigh C. Anderson , Nicolas B. Cobb , Laurence W. Grodd , Emile Sahouria , Siqiong You
发明人： Leigh C. Anderson , Nicolas B. Cobb , Laurence W. Grodd , Emile Sahouria , Siqiong You
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/26
摘要： An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.

30. 发明授权

US06425113B1 Integrated verification and manufacturability tool 有权
标题翻译：集成验证和可制造性工具
公开(公告)号：US06425113B1
公开(公告)日：2002-07-23
申请号：US09593923
申请日：2000-06-13
申请人： Leigh C. Anderson , Nicolas Bailey Cobb , Laurence W. Grodd , Emile Sahouria
发明人： Leigh C. Anderson , Nicolas Bailey Cobb , Laurence W. Grodd , Emile Sahouria
IPC分类号： G06F1750
CPC分类号： G06F17/5081 , G03F1/26
摘要： An integrated verification and manufacturability provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database for multiple verification steps streamlines the verification process, which provides an improved verification tool.
摘要翻译：集成的验证和可制造性提供了集成设备设计的更有效的验证，而不是使用几种不同的验证工具进行验证。集成验证和可制造性包括分层数据库，用于存储由多个验证工具组件访问的设计数据（例如，布局与原理图，设计规则检查，光学处理校正，相移掩模分配）。分层数据库包括一个或多个附加的或中间层结构的表示，其由验证工具组件创建并用于在被验证的设计上执行的操作。使用单个分层数据库进行多个验证步骤简化了验证过程，从而提供了一种改进的验证工具。

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