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1. 发明授权

US06415421B1 Integrated verification and manufacturability tool 有权
公开(公告)号：US06415421B1
公开(公告)日：2002-07-02
申请号：US09747190
申请日：2000-12-22
申请人： Leigh C. Anderson , Nicolas B. Cobb , Laurence W. Grodd , Emile Sahouria , Siqiong You
发明人： Leigh C. Anderson , Nicolas B. Cobb , Laurence W. Grodd , Emile Sahouria , Siqiong You
IPC分类号： G06F1750
摘要： An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.

2. 发明授权

US07017141B2 Integrated verification and manufacturability tool 有权
公开(公告)号：US07017141B2
公开(公告)日：2006-03-21
申请号：US10112223
申请日：2002-03-27
申请人： Leigh C. Anderson , Nicolas B. Cobb , Laurence W. Grodd , Emile Sahouria , Siqiong You
发明人： Leigh C. Anderson , Nicolas B. Cobb , Laurence W. Grodd , Emile Sahouria , Siqiong You
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/26
摘要： An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.

3. 发明授权

US06668367B2 Selective promotion for resolution enhancement techniques 有权
公开(公告)号：US06668367B2
公开(公告)日：2003-12-23
申请号：US10057309
申请日：2002-01-24
申请人： Nicolas B. Cobb , Laurence W. Grodd , George P. Lippincott , Emile Sahouria
发明人： Nicolas B. Cobb , Laurence W. Grodd , George P. Lippincott , Emile Sahouria
IPC分类号： G06F1750
CPC分类号： G03F1/36
摘要： A tool for optimizing the layout of a microdevice adds fragmentation points to polygons in a first hierarchical database layer in a manner suitable for application of a tool to apply a resolution enhancement technique (RET) such as optical and process correction (OPC). Portions of polygons in a database level that interact with polygons of a second level in the database are promoted to the second database level, and refragmented. The RET operates on the polygons of the first and second levels of the database to determine how polygons of each of the first and second levels should be adjusted, if necessary, such that the layout is optimized.

4. 发明授权

US07240321B2 Selective promotion for resolution enhancement techniques 有权
标题翻译：选择性推广分辨率增强技术
公开(公告)号：US07240321B2
公开(公告)日：2007-07-03
申请号：US10730765
申请日：2003-12-08
申请人： Nicolas B. Cobb , Laurence W. Grodd , George P. Lippincott , Emile Sahouria
发明人： Nicolas B. Cobb , Laurence W. Grodd , George P. Lippincott , Emile Sahouria
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A tool for optimizing the layout of a microdevice adds fragmentation points to polygons in a first hierarchical database layer in a manner suitable for application of a tool to apply a resolution enhancement technique (RET) such as optical and process correction (OPC). Portions of polygons in a database level that interact with polygons of a second level in the database are promoted to the second database level, and refragmented. The RET operates on the polygons of the first and second levels of the database to determine how polygons of each of the first and second levels should be adjusted, if necessary, such that the layout is optimized.
摘要翻译：用于优化微设备的布局的工具以适于应用工具以应用诸如光学和过程校正（OPC）的分辨率增强技术（RET）的方式向第一分层数据库层中的多边形添加碎片点。与数据库中第二级多边形交互的数据库级别中的多边形部分将升级到第二个数据库级别，并进行重新碎片整理。 RET对数据库的第一和第二级别的多边形进行操作，以确定如果需要，如何调整第一级和第二级中的每一级的多边形，使得布局被优化。

5. 发明授权

US06425113B1 Integrated verification and manufacturability tool 有权
标题翻译：集成验证和可制造性工具
公开(公告)号：US06425113B1
公开(公告)日：2002-07-23
申请号：US09593923
申请日：2000-06-13
申请人： Leigh C. Anderson , Nicolas Bailey Cobb , Laurence W. Grodd , Emile Sahouria
发明人： Leigh C. Anderson , Nicolas Bailey Cobb , Laurence W. Grodd , Emile Sahouria
IPC分类号： G06F1750
CPC分类号： G06F17/5081 , G03F1/26
摘要： An integrated verification and manufacturability provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database for multiple verification steps streamlines the verification process, which provides an improved verification tool.
摘要翻译：集成的验证和可制造性提供了集成设备设计的更有效的验证，而不是使用几种不同的验证工具进行验证。集成验证和可制造性包括分层数据库，用于存储由多个验证工具组件访问的设计数据（例如，布局与原理图，设计规则检查，光学处理校正，相移掩模分配）。分层数据库包括一个或多个附加的或中间层结构的表示，其由验证工具组件创建并用于在被验证的设计上执行的操作。使用单个分层数据库进行多个验证步骤简化了验证过程，从而提供了一种改进的验证工具。

6. 发明授权

US06901574B2 Data management method for mask writing 有权
标题翻译：面具书写数据管理方法
公开(公告)号：US06901574B2
公开(公告)日：2005-05-31
申请号：US09781128
申请日：2001-02-09
申请人： Patrick J. LaCour , Emile Sahouria , Siqiong You
发明人： Patrick J. LaCour , Emile Sahouria , Siqiong You
IPC分类号： G03F1/00 , H01L21/027 , G06F17/50 , G03C5/00 , G03F9/00 , G06F9/45 , G06F9/455
CPC分类号： G03F1/68
摘要： A method of translating device layout data to a format for a mask writing tool includes the acts of reading a file defining a number of cells that represent structures on the device. One or more cells are selected and one or more modified cells based on the interaction of the selected cells with other cells in the device layout are created. One or more additional cells is created that will create structures on the mask that are not formed by writing files corresponding to the modified cells and areas that prevent extraneous structures from being formed on the mask at a selected location by the writing of the files corresponding to the modified cells. A jobdeck for the mask writing tool is created that indicates where the files corresponding to modified cells and the one or more additional cells should be written to create one or more masks or reticles.
摘要翻译：将设备布局数据转换为掩模写入工具的格式的方法包括读取定义表示设备上的结构的多个单元格的文件的动作。选择一个或多个单元，并且创建基于所选单元与设备布局中的其他单元的交互的一个或多个修改单元。创建一个或多个额外的单元，其将在掩模上创建不是通过写入与修改的单元相对应的文件而形成的结构，并且通过写入对应于文件的文件来防止在选定位置上的掩模上形成外来结构的区域修饰细胞。创建面具书写工具的工作台，其指示与修改的单元格对应的文件的位置以及应写入一个或多个其他单元格以创建一个或多个掩码或掩模版。

7. 发明申请

US20090070732A1 Fracture Shot Count Reduction 审中-公开
标题翻译：断裂射击计数减少
公开(公告)号：US20090070732A1
公开(公告)日：2009-03-12
申请号：US11925606
申请日：2007-10-26
申请人： Emile Sahouria , Jianlin Wang
发明人： Emile Sahouria , Jianlin Wang
IPC分类号： G06F17/50
CPC分类号： G03F7/70433 , G03F1/36 , G03F1/68
摘要： Techniques are described for reducing the number of shots in a fractured layout design. Each polygon in a layout design is examined for “jogs.” For each identified jog, the surrounding region is examined to determine if there is an opposing jog or parallel edge that can be aligned with the identified jog. The surrounding region then is examined for any polygon features, such as edges or vertices, which might restrict or prevent the alignment of the identified jog with the opposing jog or edge. If the identified jog can be aligned with an opposing jog or edge without violating a specified alignment constraint, then those jogs are deemed an alignable jog pair. Next, one or more of the alignable jog pairs is selected for alignment. The alignable jog pairs may be selected for alignment based upon their impact on the size of the polygon when aligned. Once one or more of the alignable jog pairs have been selected, then the layout design data will be modified to align the selected jog pairs.
摘要翻译：描述了用于减少断裂布局设计中的拍摄张数的技术。检查布局设计中的每个多边形的“慢跑”。对于每个识别的点动，检查周围区域以确定是否存在可以与所识别的点动对准的相对的点动或平行边缘。然后检查周围区域的任何多边形特征，例如边缘或顶点，其可以限制或阻止所识别的慢跑与相对的点动或边缘的对准。如果识别的点动可以与相对的点动或边缘对齐，而不违反指定的对准约束，则这些点动被认为是可对准的点对。接下来，选择一个或多个可对准的点对对进行对准。可以选择可对准的点对对，以便在对齐时基于它们对多边形的尺寸的影响进行对准。一旦选择了一个或多个可对准的点对对，则将修改布局设计数据以对齐所选择的点对。

8. 发明授权

US07028284B2 Convergence technique for model-based optical and process correction 有权
公开(公告)号：US07028284B2
公开(公告)日：2006-04-11
申请号：US10147280
申请日：2002-05-15
申请人： Nicolas Bailey Cobb , Emile Sahouria
发明人： Nicolas Bailey Cobb , Emile Sahouria
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/70 , G06F17/5081
摘要： Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle layout to a target layout, while backward mapping refers to mapping of fragments from the target layout to the reticle layout. Forward mapping provides a technique for making an unambiguous mapping for each reticle fragment to a corresponding target layout fragment. The mapping does not necessarily provide a one-to-one correspondence between reticle fragments and target layout fragments. That is, multiple reticle layout fragments can map to a single target layout fragment. An edge placement error for the target layout fragments is used to make positioning corrections for the corresponding reticle fragment(s). Edge placement error can be determined, for example, with a simulation process that simulates a manufacturing process using the reticles.

9. 发明申请

US20100218159A1 Data Flow Branching in Mask Data Preparation 审中-公开
标题翻译：数据流分布在掩模数据准备中
公开(公告)号：US20100218159A1
公开(公告)日：2010-08-26
申请号：US12622402
申请日：2009-11-19
申请人： Emile Sahouria
发明人： Emile Sahouria
IPC分类号： G06F17/50
CPC分类号： G03F1/68
摘要： Branching of the data-flow in a mask data preparation processes is described herein. In various implementations, the output stream from a first mask data processing operation is branched. Subsequently, the branched output stream may be connected to the input stream of a first independent mask data preparation operation and a second independent mask data preparation operation. This provides that the first and the second independent mask data preparation operations may operate in parallel. Furthermore, this provides that the first and the second independent mask data preparation operations may operate upon discrete “portions” of the data processed by the first mask data preparation operation.
摘要翻译：本文描述了在掩模数据准备过程中数据流的分支。在各种实现中，来自第一掩码数据处理操作的输出流被分支。随后，分支输出流可以连接到第一独立掩模数据准备操作和第二独立掩模数据准备操作的输入流。这提供了第一和第二独立掩模数据准备操作可以并行操作。此外，这提供了第一和第二独立掩模数据准备操作可以对由第一掩模数据准备操作处理的数据的离散“部分”进行操作。

10. 发明授权

US08516401B2 Mask model calibration technologies involving etch effect and exposure effect 有权
标题翻译：掩模模型校准技术涉及蚀刻效应和曝光效果
公开(公告)号：US08516401B2
公开(公告)日：2013-08-20
申请号：US12622114
申请日：2009-11-19
申请人： Emile Sahouria , Yuanfang Hu
发明人： Emile Sahouria , Yuanfang Hu
IPC分类号： G06F17/50
CPC分类号： G03F1/68
摘要： Methods for jointly calibrating etch and exposure mask process models from etch only data are described. Initially, an etch model and an exposure model may be identified. Subsequently, a combined etch/exposure model may be generated based upon the etch model and the exposure model. Following which, a global optimization process may be performed to calibrate the combined etch/exposure model based upon measured data representing the etch and the exposure effects. With some implementations, the global optimization process is based in part upon a cost function representing the norm of the difference between the simulated mask contours and the measured mask contours. Furthermore, in some implementations, the optimization variable set is the union of the parameter sets corresponding to the etch model and the exposure model individually. Further still, with various implementations, the optimization of based upon the etch parameter set is “nested” inside an optimization of the exposure parameter set, or, vice versa.
摘要翻译：描述了仅从蚀刻数据共同校准蚀刻和曝光掩模工艺模型的方法。最初，可以识别蚀刻模型和曝光模型。随后，可以基于蚀刻模型和曝光模型来生成组合的蚀刻/曝光模型。随后，可以基于表示蚀刻和曝光效果的测量数据来执行全局优化处理以校准组合的蚀刻/曝光模型。通过一些实现，全局优化过程部分地基于代表模拟掩模轮廓和所测量的掩模轮廓之间的差异范围的成本函数。此外，在一些实施方案中，优化变量集合是分别对应于蚀刻模型和曝光模型的参数集的并集。此外，通过各种实现，基于蚀刻参数集的优化在曝光参数集的优化内“嵌套”，或反之亦然。

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